sd card logging working

This commit is contained in:
ggw
2026-05-05 18:17:02 -05:00
parent 90cd2273f1
commit c9d0ff0686
15 changed files with 100 additions and 403 deletions
+10
View File
@@ -64,6 +64,11 @@ struct packet_spo2 {
uint32_t ir_cnts[25];
};
struct packet_msg {
uint32_t t;
char buff[32];
};
template<typename T>
__inline__ uint8_t typecode() {
return 0;
@@ -113,3 +118,8 @@ template<>
__inline__ uint8_t typecode<struct packet_imu>() {
return 9;
}
template<>
__inline__ uint8_t typecode<struct packet_msg>() {
return 10;
}
-1
View File
@@ -67,7 +67,6 @@ void USART1_IRQHandler(void);
void SDMMC1_IRQHandler(void);
void TIM6_DAC_IRQHandler(void);
void DMA2_Channel4_IRQHandler(void);
void DMA2_Channel5_IRQHandler(void);
void USB_IRQHandler(void);
/* USER CODE BEGIN EFP */
+2 -2
View File
@@ -1,6 +1,6 @@
//#include "buff.hpp"
#include <cstdint>
uint8_t databank1[1024];
uint8_t databank2[1024];
alignas(32) uint8_t databank1[1024];
alignas(32) uint8_t databank2[1024];
uint16_t pos = 0;
@@ -56,4 +56,9 @@ void data_description(bool to_usb, bool to_file) {
if (to_usb) {CDC_Transmit_FS((uint8_t*)buff, cx);}
HAL_Delay(50);
cx = snprintf(buff, sizeof(buff), "%s %d %d %s %d %d %s %d %d\n\r", "packet_msg", typecode<packet_msg>(), sizeof(packet_msg), "uint32_t t", offsetof(packet_msg, t), sizeof(uint32_t), "char buff[32]", offsetof(packet_msg, buff), sizeof(char));
if (to_file) {unsigned int bw; f_write(&file, buff, cx, &bw);}
if (to_usb) {CDC_Transmit_FS((uint8_t*)buff, cx);}
HAL_Delay(50);
}
-3
View File
@@ -53,9 +53,6 @@ void MX_DMA_Init(void)
/* DMA2_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Channel4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Channel4_IRQn);
/* DMA2_Channel5_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Channel5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Channel5_IRQn);
}
+9 -16
View File
@@ -125,7 +125,6 @@ void USB_CDC_RxHandler(uint8_t* Buf, uint32_t Len) {
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
if (uart_rx_data[0] == 'R') {
//HAL_GPIO_TogglePin(GPIOB, LED1_Pin | LED2_Pin | LED3_Pin);
wb1mmc_ready = true;
}
HAL_UART_Receive_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
@@ -136,37 +135,28 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {}
void turn_on_sd(void) {
to_turn_on_sd = false;
if (BSP_SD_IsDetected() != SD_PRESENT) {
CDC_Transmit_FS((uint8_t*)"SD NP\n\r", 7);
return;
}
if (sd_ready) {
CDC_Transmit_FS((uint8_t*)"SD RD\n\r", 7);
return;
}
if ((BSP_SD_IsDetected() == SD_PRESENT) && (!sd_ready)) {
CDC_Transmit_FS((uint8_t*)"HERE1\n\r", 7);
res = f_mount(&fs, "", 1);
if (res != FR_OK) {
CDC_Transmit_FS((uint8_t*)"SD NOK1\n\r", 9);
return;
}
CDC_Transmit_FS((uint8_t*)"HERE2\n\r", 7);
alignas(32) char buffer1[32];
alignas(32) char buffer2[32];
int cx = snprintf(buffer1, 32, "%06lu.log", TIM6->CNT);
int cx = snprintf(buffer1, 32, "%08lu.log", ((uint32_t)tim6_reloads) * (htim6.Init.Period + 1) + TIM6->CNT % 99999999);
cx = snprintf(buffer2, 32, "%s\n\r", buffer1);
CDC_Transmit_FS((uint8_t*)buffer2, cx);
res = f_open(&file, buffer1, FA_WRITE | FA_CREATE_ALWAYS);
if (res != FR_OK) {
CDC_Transmit_FS((uint8_t*)"SD NOK2\n\r", 9);
res = f_mount(NULL, "", 1);
return;
}
CDC_Transmit_FS((uint8_t*)"SUCCESS\n\r", 9);
unsigned int bw;
res = f_write(&file, "HERE\n\r", 6, &bw);
cx = snprintf(buffer2, 32, "%d %d\n\r", res, bw);
CDC_Transmit_FS((uint8_t*)buffer2, cx);
//data_description(false, true);
data_description(false, true);
sd_ready = true;
}
}
@@ -217,7 +207,6 @@ int main(void)
MX_GPIO_Init();
MX_DMA_Init();
MX_SDMMC1_SD_Init();
MX_FATFS_Init();
MX_RTC_Init();
MX_I2C1_Init();
MX_SPI1_Init();
@@ -226,17 +215,21 @@ int main(void)
MX_USART1_UART_Init();
MX_TIM6_Init();
MX_USB_DEVICE_Init();
MX_FATFS_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
HAL_TIM_Base_Start_IT(&htim6);
HAL_UART_Receive_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
//HAL_UART_Receive_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
// For some reason initializing the ads131 first breaks the lsm6dsv gyro readings
initialize_lsm6dsv(&hspi1);
initialize_ads131(&hspi1);
HAL_Delay(3000);
uint8_t buf[512];
while (1)
{
if (to_turn_on_sd) {
+19 -32
View File
@@ -25,8 +25,7 @@
/* USER CODE END 0 */
SD_HandleTypeDef hsd1;
DMA_HandleTypeDef hdma_sdmmc1_rx;
DMA_HandleTypeDef hdma_sdmmc1_tx;
DMA_HandleTypeDef hdma_sdmmc1;
/* SDMMC1 init function */
@@ -46,7 +45,7 @@ void MX_SDMMC1_SD_Init(void)
hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
hsd1.Init.ClockDiv = 0;
hsd1.Init.ClockDiv = 6;
/* USER CODE BEGIN SDMMC1_Init 2 */
/* USER CODE END SDMMC1_Init 2 */
@@ -91,39 +90,27 @@ void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* SDMMC1 DMA Init */
/* SDMMC1_RX Init */
hdma_sdmmc1_rx.Instance = DMA2_Channel4;
hdma_sdmmc1_rx.Init.Request = DMA_REQUEST_7;
hdma_sdmmc1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_sdmmc1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sdmmc1_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_sdmmc1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_sdmmc1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_sdmmc1_rx.Init.Mode = DMA_NORMAL;
hdma_sdmmc1_rx.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_sdmmc1_rx) != HAL_OK)
/* SDMMC1 Init */
hdma_sdmmc1.Instance = DMA2_Channel4;
hdma_sdmmc1.Init.Request = DMA_REQUEST_7;
hdma_sdmmc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_sdmmc1.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sdmmc1.Init.MemInc = DMA_MINC_ENABLE;
hdma_sdmmc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_sdmmc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_sdmmc1.Init.Mode = DMA_NORMAL;
hdma_sdmmc1.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_sdmmc1) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(sdHandle,hdmarx,hdma_sdmmc1_rx);
/* SDMMC1_TX Init */
hdma_sdmmc1_tx.Instance = DMA2_Channel5;
hdma_sdmmc1_tx.Init.Request = DMA_REQUEST_7;
hdma_sdmmc1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_sdmmc1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_sdmmc1_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_sdmmc1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_sdmmc1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_sdmmc1_tx.Init.Mode = DMA_NORMAL;
hdma_sdmmc1_tx.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_sdmmc1_tx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(sdHandle,hdmatx,hdma_sdmmc1_tx);
/* Several peripheral DMA handle pointers point to the same DMA handle.
Be aware that there is only one channel to perform all the requested DMAs. */
/* Be sure to change transfer direction before calling
HAL_SD_ReadBlocks_DMA or HAL_SD_WriteBlocks_DMA. */
__HAL_LINKDMA(sdHandle,hdmarx,hdma_sdmmc1);
__HAL_LINKDMA(sdHandle,hdmatx,hdma_sdmmc1);
/* SDMMC1 interrupt Init */
HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
+2 -17
View File
@@ -58,8 +58,7 @@
extern PCD_HandleTypeDef hpcd_USB_FS;
extern ADC_HandleTypeDef hadc1;
extern I2C_HandleTypeDef hi2c1;
extern DMA_HandleTypeDef hdma_sdmmc1_rx;
extern DMA_HandleTypeDef hdma_sdmmc1_tx;
extern DMA_HandleTypeDef hdma_sdmmc1;
extern SD_HandleTypeDef hsd1;
extern SPI_HandleTypeDef hspi1;
extern TIM_HandleTypeDef htim6;
@@ -371,26 +370,12 @@ void DMA2_Channel4_IRQHandler(void)
/* USER CODE BEGIN DMA2_Channel4_IRQn 0 */
/* USER CODE END DMA2_Channel4_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_sdmmc1_rx);
HAL_DMA_IRQHandler(&hdma_sdmmc1);
/* USER CODE BEGIN DMA2_Channel4_IRQn 1 */
/* USER CODE END DMA2_Channel4_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel5 global interrupt.
*/
void DMA2_Channel5_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel5_IRQn 0 */
/* USER CODE END DMA2_Channel5_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_sdmmc1_tx);
/* USER CODE BEGIN DMA2_Channel5_IRQn 1 */
/* USER CODE END DMA2_Channel5_IRQn 1 */
}
/**
* @brief This function handles USB event interrupt through EXTI line 17.
*/
-12
View File
@@ -37,18 +37,6 @@ void MX_FATFS_Init(void)
/* USER CODE END Init */
}
/**
* @brief Gets Time from RTC
* @param None
* @retval Time in DWORD
*/
DWORD get_fattime(void)
{
/* USER CODE BEGIN get_fattime */
return 0;
/* USER CODE END get_fattime */
}
/* USER CODE BEGIN Application */
/* USER CODE END Application */
+1 -1
View File
@@ -214,7 +214,7 @@
/ When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
/ Note that enabling exFAT discards C89 compatibility. */
#define _FS_NORTC 0
#define _FS_NORTC 1
#define _NORTC_MON 6
#define _NORTC_MDAY 4
#define _NORTC_YEAR 2015
+24 -286
View File
@@ -17,8 +17,8 @@
*/
/* USER CODE END Header */
/* Note: code generation based on sd_diskio_dma_template_bspv1.c v2.1.4
as "Use dma template" is enabled. */
/* Note: code generation based on sd_diskio_template_bspv1.c v2.1.4
as "Use dma template" is disabled. */
/* USER CODE BEGIN firstSection */
/* can be used to modify / undefine following code or add new definitions */
@@ -28,17 +28,16 @@
#include "ff_gen_drv.h"
#include "sd_diskio.h"
#include <string.h>
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/*
* the following Timeout is useful to give the control back to the applications
* in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback()
* the value by default is as defined in the BSP platform driver otherwise 30 secs
*/
/* use the default SD timout as defined in the platform BSP driver*/
#if defined(SDMMC_DATATIMEOUT)
#define SD_TIMEOUT SDMMC_DATATIMEOUT
#elif defined(SD_DATATIMEOUT)
#define SD_TIMEOUT SD_DATATIMEOUT
#else
#define SD_TIMEOUT 30 * 1000
#endif
#define SD_DEFAULT_BLOCK_SIZE 512
@@ -52,37 +51,10 @@
/* #define DISABLE_SD_INIT */
/* USER CODE END disableSDInit */
/*
* when using cacheable memory region, it may be needed to maintain the cache
* validity. Enable the define below to activate a cache maintenance at each
* read and write operation.
* Notice: This is applicable only for cortex M7 based platform.
*/
/* USER CODE BEGIN enableSDDmaCacheMaintenance */
/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE 1 */
/* USER CODE END enableSDDmaCacheMaintenance */
/*
* Some DMA requires 4-Byte aligned address buffer to correctly read/write data,
* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly
* transfer data
*/
/* USER CODE BEGIN enableScratchBuffer */
/* #define ENABLE_SCRATCH_BUFFER */
/* USER CODE END enableScratchBuffer */
/* Private variables ---------------------------------------------------------*/
#if defined(ENABLE_SCRATCH_BUFFER)
#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE)
ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance
#else
__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END;
#endif
#endif
/* Disk status */
static volatile DSTATUS Stat = STA_NOINIT;
static volatile UINT WriteStatus = 0, ReadStatus = 0;
/* Private function prototypes -----------------------------------------------*/
static DSTATUS SD_CheckStatus(BYTE lun);
DSTATUS SD_initialize (BYTE);
@@ -115,21 +87,6 @@ const Diskio_drvTypeDef SD_Driver =
/* Private functions ---------------------------------------------------------*/
static int SD_CheckStatusWithTimeout(uint32_t timeout)
{
uint32_t timer = HAL_GetTick();
/* block until SDIO IP is ready again or a timeout occur */
while(HAL_GetTick() - timer < timeout)
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
{
return 0;
}
}
return -1;
}
static DSTATUS SD_CheckStatus(BYTE lun)
{
Stat = STA_NOINIT;
@@ -149,6 +106,7 @@ static DSTATUS SD_CheckStatus(BYTE lun)
*/
DSTATUS SD_initialize(BYTE lun)
{
Stat = STA_NOINIT;
#if !defined(DISABLE_SD_INIT)
@@ -189,108 +147,17 @@ DSTATUS SD_status(BYTE lun)
DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_ERROR;
uint32_t timeout;
#if defined(ENABLE_SCRATCH_BUFFER)
uint8_t ret;
#endif
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
uint32_t alignedAddr;
#endif
/*
* ensure the SDCard is ready for a new operation
*/
if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
if(BSP_SD_ReadBlocks((uint32_t*)buff,
(uint32_t) (sector),
count, SD_TIMEOUT) == MSD_OK)
{
return res;
}
#if defined(ENABLE_SCRATCH_BUFFER)
if (!((uint32_t)buff & 0x3))
{
#endif
if(BSP_SD_ReadBlocks_DMA((uint32_t*)buff,
(uint32_t) (sector),
count) == MSD_OK)
/* wait until the read operation is finished */
while(BSP_SD_GetCardState()!= MSD_OK)
{
ReadStatus = 0;
/* Wait that the reading process is completed or a timeout occurs */
timeout = HAL_GetTick();
while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
{
}
/* in case of a timeout return error */
if (ReadStatus == 0)
{
res = RES_ERROR;
}
else
{
ReadStatus = 0;
timeout = HAL_GetTick();
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
{
res = RES_OK;
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
/*
the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address,
adjust the address and the D-Cache size to invalidate accordingly.
*/
alignedAddr = (uint32_t)buff & ~0x1F;
SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
#endif
break;
}
}
}
}
#if defined(ENABLE_SCRATCH_BUFFER)
res = RES_OK;
}
else
{
/* Slow path, fetch each sector a part and memcpy to destination buffer */
int i;
for (i = 0; i < count; i++) {
ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
if (ret == MSD_OK) {
/* wait until the read is successful or a timeout occurs */
timeout = HAL_GetTick();
while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
{
}
if (ReadStatus == 0)
{
res = RES_ERROR;
break;
}
ReadStatus = 0;
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
/*
*
* invalidate the scratch buffer before the next read to get the actual data instead of the cached one
*/
SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
#endif
memcpy(buff, scratch, BLOCKSIZE);
buff += BLOCKSIZE;
}
else
{
break;
}
}
if ((i == count) && (ret == MSD_OK))
res = RES_OK;
}
#endif
return res;
}
@@ -311,107 +178,18 @@ DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
{
DRESULT res = RES_ERROR;
uint32_t timeout;
#if defined(ENABLE_SCRATCH_BUFFER)
uint8_t ret;
int i;
#endif
WriteStatus = 0;
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
uint32_t alignedAddr;
#endif
if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
if(BSP_SD_WriteBlocks((uint32_t*)buff,
(uint32_t)(sector),
count, SD_TIMEOUT) == MSD_OK)
{
return res;
/* wait until the Write operation is finished */
while(BSP_SD_GetCardState() != MSD_OK)
{
}
res = RES_OK;
}
#if defined(ENABLE_SCRATCH_BUFFER)
if (!((uint32_t)buff & 0x3))
{
#endif
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
/*
the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address
adjust the address and the D-Cache size to clean accordingly.
*/
alignedAddr = (uint32_t)buff & ~0x1F;
SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
#endif
if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff,
(uint32_t)(sector),
count) == MSD_OK)
{
/* Wait that writing process is completed or a timeout occurs */
timeout = HAL_GetTick();
while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
{
}
/* in case of a timeout return error */
if (WriteStatus == 0)
{
res = RES_ERROR;
}
else
{
WriteStatus = 0;
timeout = HAL_GetTick();
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
{
res = RES_OK;
break;
}
}
}
}
#if defined(ENABLE_SCRATCH_BUFFER)
}
else
{
/* Slow path, fetch each sector a part and memcpy to destination buffer */
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
/*
* invalidate the scratch buffer before the next write to get the actual data instead of the cached one
*/
SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
#endif
for (i = 0; i < count; i++)
{
WriteStatus = 0;
memcpy((void *)scratch, (void *)buff, BLOCKSIZE);
buff += BLOCKSIZE;
ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
if (ret == MSD_OK) {
/* wait for a message from the queue or a timeout */
timeout = HAL_GetTick();
while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
{
}
if (WriteStatus == 0)
{
break;
}
}
else
{
break;
}
}
if ((i == count) && (ret == MSD_OK))
res = RES_OK;
}
#endif
return res;
}
#endif /* _USE_WRITE == 1 */
@@ -474,46 +252,6 @@ DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
/* can be used to modify previous code / undefine following code / add new code */
/* USER CODE END afterIoctlSection */
/* USER CODE BEGIN callbackSection */
/* can be used to modify / following code or add new code */
/* USER CODE END callbackSection */
/**
* @brief Tx Transfer completed callbacks
* @param hsd: SD handle
* @retval None
*/
void BSP_SD_WriteCpltCallback(void)
{
WriteStatus = 1;
}
/**
* @brief Rx Transfer completed callbacks
* @param hsd: SD handle
* @retval None
*/
void BSP_SD_ReadCpltCallback(void)
{
ReadStatus = 1;
}
/* USER CODE BEGIN ErrorAbortCallbacks */
/*
==============================================================================================
depending on the SD_HAL_Driver version, either the HAL_SD_ErrorCallback() or HAL_SD_AbortCallback()
or both could be defined, activate the callbacks below when suitable and needed
==============================================================================================
void BSP_SD_AbortCallback(void)
{
}
void BSP_SD_ErrorCallback(void)
{
}
*/
/* USER CODE END ErrorAbortCallbacks */
/* USER CODE BEGIN lastSection */
/* can be used to modify / undefine previous code or add new code */
/* USER CODE END lastSection */
+1 -1
View File
@@ -17,7 +17,7 @@
*/
/* USER CODE END Header */
/* Note: code generation based on sd_diskio_dma_template.h */
/* Note: code generation based on sd_diskio_template.h */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SD_DISKIO_H
+5 -5
View File
@@ -1,5 +1,5 @@
##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [4.9.0-B19] date: [Tue May 05 14:07:50 CDT 2026]
# File automatically-generated by tool: [projectgenerator] version: [4.9.0-B19] date: [Tue May 05 18:08:47 CDT 2026]
##########################################################################################################################
# ------------------------------------------------
@@ -150,17 +150,17 @@ AS_INCLUDES =
# C includes
C_INCLUDES = \
-ICore/Inc \
-IFATFS/Target \
-IFATFS/App \
-IDrivers/STM32L4xx_HAL_Driver/Inc \
-IDrivers/STM32L4xx_HAL_Driver/Inc/Legacy \
-IMiddlewares/Third_Party/FatFs/src \
-IDrivers/CMSIS/Device/ST/STM32L4xx/Include \
-IDrivers/CMSIS/Include \
-IUSB_DEVICE/App \
-IUSB_DEVICE/Target \
-IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \
-IMiddlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc
-IMiddlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc \
-IFATFS/Target \
-IFATFS/App \
-IMiddlewares/Third_Party/FatFs/src
# compile gcc flags
+1 -1
View File
@@ -91,7 +91,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
__HAL_RCC_USB_CLK_ENABLE();
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_IRQn, 0, 0);
HAL_NVIC_SetPriority(USB_IRQn, 7, 0);
HAL_NVIC_EnableIRQ(USB_IRQn);
/* USER CODE BEGIN USB_MspInit 1 */
+21 -26
View File
@@ -12,27 +12,17 @@ CAD.pinconfig=
CAD.provider=
Dma.Request0=USART1_RX
Dma.Request1=USART1_TX
Dma.Request2=SDMMC1_RX
Dma.Request3=SDMMC1_TX
Dma.RequestsNb=4
Dma.SDMMC1_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDMMC1_RX.2.Instance=DMA2_Channel4
Dma.SDMMC1_RX.2.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_RX.2.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_RX.2.Mode=DMA_NORMAL
Dma.SDMMC1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_RX.2.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.SDMMC1_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.SDMMC1_TX.3.Instance=DMA2_Channel5
Dma.SDMMC1_TX.3.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_TX.3.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_TX.3.Mode=DMA_NORMAL
Dma.SDMMC1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_TX.3.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.Request2=SDMMC1
Dma.RequestsNb=3
Dma.SDMMC1.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDMMC1.2.Instance=DMA2_Channel4
Dma.SDMMC1.2.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1.2.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1.2.Mode=DMA_NORMAL
Dma.SDMMC1.2.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1.2.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1.2.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.0.Instance=DMA1_Channel5
Dma.USART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
@@ -52,8 +42,11 @@ Dma.USART1_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.1.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
FATFS.BSP.number=1
FATFS.IPParameters=USE_DMA_CODE_SD
FATFS.USE_DMA_CODE_SD=1
FATFS.IPParameters=USE_DMA_CODE_SD,_USE_LFN,_MAX_SS,_FS_NORTC
FATFS.USE_DMA_CODE_SD=0
FATFS._FS_NORTC=1
FATFS._MAX_SS=512
FATFS._USE_LFN=0
FATFS0.BSP.STBoard=false
FATFS0.BSP.api=Unknown
FATFS0.BSP.component=
@@ -137,7 +130,6 @@ NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.EXTI3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
@@ -155,7 +147,7 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.USB_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.USB_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA0.GPIOParameters=GPIO_Label
PA0.GPIO_Label=CLKIN_ADC
@@ -285,7 +277,7 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,5-MX_FATFS_Init-FATFS-false-HAL-false,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_I2C1_Init-I2C1-false-HAL-true,8-MX_SPI1_Init-SPI1-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_TIM2_Init-TIM2-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_TIM6_Init-TIM6-false-HAL-true,13-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_TIM2_Init-TIM2-false-HAL-true,10-MX_USART1_UART_Init-USART1-false-HAL-true,11-MX_TIM6_Init-TIM6-false-HAL-true,12-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,13-MX_FATFS_Init-FATFS-false-HAL-false
RCC.ADCFreq_Value=48000000
RCC.AHBFreq_Value=80000000
RCC.APB1Freq_Value=80000000
@@ -335,6 +327,9 @@ RCC.USBFreq_Value=48000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=160000000
RCC.VCOSAI1OutputFreq_Value=96000000
SDMMC1.ClockDiv=6
SDMMC1.ClockEdge=SDMMC_CLOCK_EDGE_RISING
SDMMC1.IPParameters=ClockDiv,ClockEdge
SH.ADCx_IN16.0=ADC1_IN16,IN16-Single-Ended
SH.ADCx_IN16.ConfNb=1
SH.GPXTI0.0=GPIO_EXTI0