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ggw
2026-05-05 14:09:15 -05:00
parent 42f91eb075
commit 90cd2273f1
16 changed files with 835 additions and 96 deletions
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code/l452_code/l452_code.ioc
+25 -1
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@@ -12,7 +12,27 @@ CAD.pinconfig=
CAD.provider=
Dma.Request0=USART1_RX
Dma.Request1=USART1_TX
Dma.RequestsNb=2
Dma.Request2=SDMMC1_RX
Dma.Request3=SDMMC1_TX
Dma.RequestsNb=4
Dma.SDMMC1_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.SDMMC1_RX.2.Instance=DMA2_Channel4
Dma.SDMMC1_RX.2.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_RX.2.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_RX.2.Mode=DMA_NORMAL
Dma.SDMMC1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_RX.2.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.SDMMC1_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.SDMMC1_TX.3.Instance=DMA2_Channel5
Dma.SDMMC1_TX.3.MemDataAlignment=DMA_MDATAALIGN_WORD
Dma.SDMMC1_TX.3.MemInc=DMA_MINC_ENABLE
Dma.SDMMC1_TX.3.Mode=DMA_NORMAL
Dma.SDMMC1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_WORD
Dma.SDMMC1_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.SDMMC1_TX.3.Priority=DMA_PRIORITY_LOW
Dma.SDMMC1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.0.Instance=DMA1_Channel5
Dma.USART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
@@ -32,6 +52,8 @@ Dma.USART1_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.1.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
FATFS.BSP.number=1
FATFS.IPParameters=USE_DMA_CODE_SD
FATFS.USE_DMA_CODE_SD=1
FATFS0.BSP.STBoard=false
FATFS0.BSP.api=Unknown
FATFS0.BSP.component=
@@ -114,6 +136,8 @@ NVIC.ADC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.EXTI3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true