log fix (added f_extend), other changes
This commit is contained in:
@@ -1,440 +0,0 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file app_debug.c
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* @author MCD Application Team
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* @brief Debug capabilities source file for STM32WPAN Middleware
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#include "app_common.h"
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#include "app_debug.h"
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#include "utilities_common.h"
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#include "shci.h"
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#include "tl.h"
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#include "dbg_trace.h"
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#include "standby.h"
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN PTD */
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typedef PACKED_STRUCT
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{
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GPIO_TypeDef* port;
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uint16_t pin;
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uint8_t enable;
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uint8_t reserved;
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} APPD_GpioConfig_t;
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/* USER CODE END PTD */
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/* Private defines -----------------------------------------------------------*/
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/* USER CODE BEGIN PD */
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#define GPIO_NBR_OF_RF_SIGNALS 9
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#define GPIO_CFG_NBR_OF_FEATURES 38
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#define NBR_OF_TRACES_CONFIG_PARAMETERS 4
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#define NBR_OF_GENERAL_CONFIG_PARAMETERS 14
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/**
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* THIS SHALL BE SET TO A VALUE DIFFERENT FROM 0 ONLY ON REQUEST FROM ST SUPPORT
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*/
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#define BLE_DTB_CFG 0
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/**
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* System Debug Options flags to be configured with:
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* - SHCI_C2_DEBUG_OPTIONS_IPCORE_LP
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* - SHCI_C2_DEBUG_OPTIONS_IPCORE_NO_LP
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* - SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_EN
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* - SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_DIS
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* which are used to set following configuration bits:
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* - bit 0: 0: IP BLE core in LP mode 1: IP BLE core in run mode (no LP supported)
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* - bit 1: 0: CPU2 STOP mode Enable 1: CPU2 STOP mode Disable
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* - bit [2-7]: bits reserved ( shall be set to 0)
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*/
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#define SYS_DBG_CFG1 (SHCI_C2_DEBUG_OPTIONS_IPCORE_LP | SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_EN)
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/* USER CODE END PD */
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/* Private macros ------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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/* USER CODE BEGIN PV */
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_TracesConfig_t APPD_TracesConfig={0, 0, 0, 0};
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static SHCI_C2_DEBUG_GeneralConfig_t APPD_GeneralConfig={BLE_DTB_CFG, SYS_DBG_CFG1, {0, 0}, 0, 0, 0, 0, 0};
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#ifdef CFG_DEBUG_TRACE_UART
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#if(CFG_HW_LPUART1_ENABLED == 1)
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extern void MX_LPUART1_UART_Init(void);
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#endif
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#if(CFG_HW_USART1_ENABLED == 1)
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extern void MX_USART1_UART_Init(void);
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#endif
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#endif
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/**
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* THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
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* It provides timing information on the CPU2 activity.
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* All configuration of (port, pin) is supported for each features and can be selected by the user
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* depending on the availability
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*/
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static const APPD_GpioConfig_t aGpioConfigList[GPIO_CFG_NBR_OF_FEATURES] =
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{
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_ISR - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_STACK_TICK - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_CMD_PROCESS - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_ACL_DATA_PROCESS - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* SYS_CMD_PROCESS - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* RNG_PROCESS - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVM_PROCESS - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_GENERAL - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_CMD_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_EVT_TX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_ACL_DATA_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_SYS_CMD_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_SYS_EVT_TX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_CLI_CMD_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_OT_CMD_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_OT_ACK_TX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_CLI_ACK_TX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_MEM_MANAGER_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_TRACES_TX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* HARD_FAULT - Set on Entry / Reset on Exit */
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/* From v1.1.1 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IP_CORE_LP_STATUS - Set on Entry / Reset on Exit */
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/* From v1.2.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* END_OF_CONNECTION_EVENT - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* TIMER_SERVER_CALLBACK - Toggle on Entry */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* PES_ACTIVITY - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* MB_BLE_SEND_EVT - Set on Entry / Reset on Exit */
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/* From v1.3.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_NO_DELAY - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_STACK_STORE_NVM_CB - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_WRITE_ONGOING - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_WRITE_COMPLETE - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_CLEANUP - Set on Entry / Reset on Exit */
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/* From v1.4.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* NVMA_START - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_EOP - Set on Entry / Reset on Exit */
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/* From v1.5.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_WRITE - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* FLASH_ERASE - Set on Entry / Reset on Exit */
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/* From v1.6.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_RESCHEDULE_EVENT - Set on Entry / Reset on Exit */
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/* From v1.8.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_LLD_CMD_RX - Set on Entry / Reset on Exit */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* IPCC_BLE_LLD_ACK_TX - Set on Entry / Reset on Exit */
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/* From v1.9.0 */
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{ GPIOA, LL_GPIO_PIN_0, 0, 0}, /* BLE_ASYNCH_EVENT_NACKED - Set on Entry / Reset on Exit */
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};
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/**
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* THE DEBUG ON GPIO FOR CPU2 IS INTENDED TO BE USED ONLY ON REQUEST FROM ST SUPPORT
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* This table is relevant only for BLE
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* It provides timing information on BLE RF activity.
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* New signals may be allocated at any location when requested by ST
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* The GPIO allocated to each signal depend on the BLE_DTB_CFG value and cannot be changed
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*/
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#if( BLE_DTB_CFG == 7)
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static const APPD_GpioConfig_t aRfConfigList[GPIO_NBR_OF_RF_SIGNALS] =
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{
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{ GPIOB, LL_GPIO_PIN_2, 0, 0}, /* DTB10 - Tx/Rx SPI */
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{ GPIOB, LL_GPIO_PIN_7, 0, 0}, /* DTB11 - Tx/Tx SPI Clk */
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{ GPIOA, LL_GPIO_PIN_8, 0, 0}, /* DTB12 - Tx/Rx Ready & SPI Select */
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{ GPIOA, LL_GPIO_PIN_9, 0, 0}, /* DTB13 - Tx/Rx Start */
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{ GPIOA, LL_GPIO_PIN_10, 0, 0}, /* DTB14 - FSM0 */
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{ GPIOA, LL_GPIO_PIN_11, 0, 0}, /* DTB15 - FSM1 */
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{ GPIOB, LL_GPIO_PIN_8, 0, 0}, /* DTB16 - FSM2 */
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{ GPIOA, LL_GPIO_PIN_13, 0, 0}, /* DTB17 - FSM3 */
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{ GPIOA, LL_GPIO_PIN_14, 0, 0}, /* DTB18 - FSM4 */
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};
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#endif
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/* USER CODE END PV */
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/* Global variables ----------------------------------------------------------*/
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/* USER CODE BEGIN GV */
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/* USER CODE END GV */
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/* Private function prototypes -----------------------------------------------*/
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/* USER CODE BEGIN PFP */
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static void APPD_SetCPU2GpioConfig( void );
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static void APPD_BleDtbCfg( void );
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/* USER CODE END PFP */
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/* Functions Definition ------------------------------------------------------*/
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void APPD_Init( void )
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{
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/* USER CODE BEGIN APPD_Init */
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#if (CFG_DEBUGGER_SUPPORTED == 1)
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/**
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* Keep debugger enabled while in any low power mode
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*/
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HAL_DBGMCU_EnableDBGSleepMode();
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HAL_DBGMCU_EnableDBGStopMode();
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/***************** ENABLE DEBUGGER *************************************/
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LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
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#else
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GPIO_InitTypeDef gpio_config = {0};
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gpio_config.Pull = GPIO_NOPULL;
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gpio_config.Mode = GPIO_MODE_ANALOG;
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gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
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__HAL_RCC_GPIOA_CLK_ENABLE();
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HAL_GPIO_Init(GPIOA, &gpio_config);
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__HAL_RCC_GPIOA_CLK_DISABLE();
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gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
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__HAL_RCC_GPIOB_CLK_ENABLE();
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HAL_GPIO_Init(GPIOB, &gpio_config);
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__HAL_RCC_GPIOB_CLK_DISABLE();
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HAL_DBGMCU_DisableDBGSleepMode();
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HAL_DBGMCU_DisableDBGStopMode();
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HAL_DBGMCU_DisableDBGStandbyMode();
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#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
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#if(CFG_DEBUG_TRACE != 0)
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DbgTraceInit();
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#endif
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APPD_SetCPU2GpioConfig( );
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APPD_BleDtbCfg( );
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/* USER CODE END APPD_Init */
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return;
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}
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void APPD_EnableCPU2( void )
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{
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/* USER CODE BEGIN APPD_EnableCPU2 */
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APPD_GeneralConfig.STBY_DebugGpioaPinList = STBY_DebugGpioaPinList;
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APPD_GeneralConfig.STBY_DebugGpiobPinList = STBY_DebugGpiobPinList;
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APPD_GeneralConfig.STBY_DebugGpiocPinList = STBY_DebugGpiocPinList;
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APPD_GeneralConfig.STBY_DtbGpioaPinList = STBY_DtbGpioaPinList;
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APPD_GeneralConfig.STBY_DtbGpiobPinList = STBY_DtbGpiobPinList;
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SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
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{
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{{0,0,0}}, /**< Does not need to be initialized */
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{(uint8_t *)aGpioConfigList,
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(uint8_t *)&APPD_TracesConfig,
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(uint8_t *)&APPD_GeneralConfig,
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GPIO_CFG_NBR_OF_FEATURES,
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NBR_OF_TRACES_CONFIG_PARAMETERS,
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NBR_OF_GENERAL_CONFIG_PARAMETERS}
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};
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/**< Traces channel initialization */
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TL_TRACES_Init( );
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/** GPIO DEBUG Initialization */
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SHCI_C2_DEBUG_Init( &DebugCmdPacket );
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/* USER CODE END APPD_EnableCPU2 */
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return;
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}
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/*************************************************************
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*
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* LOCAL FUNCTIONS
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*
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*************************************************************/
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static void APPD_SetCPU2GpioConfig( void )
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{
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/* USER CODE BEGIN APPD_SetCPU2GpioConfig */
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GPIO_InitTypeDef gpio_config = {0};
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uint8_t local_loop;
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uint16_t gpioa_pin_list;
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uint16_t gpiob_pin_list;
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uint16_t gpioc_pin_list;
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gpioa_pin_list = STBY_DebugGpioaPinList;
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gpiob_pin_list = STBY_DebugGpiobPinList;
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gpioc_pin_list = STBY_DebugGpiocPinList;
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if(gpioa_pin_list == UINT16_MAX)
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{
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gpioa_pin_list = 0;
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gpiob_pin_list = 0;
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gpioc_pin_list = 0;
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for(local_loop = 0 ; local_loop < GPIO_CFG_NBR_OF_FEATURES; local_loop++)
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{
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if( aGpioConfigList[local_loop].enable != 0)
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{
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switch((uint32_t)aGpioConfigList[local_loop].port)
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{
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case (uint32_t)GPIOA:
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gpioa_pin_list |= aGpioConfigList[local_loop].pin;
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break;
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case (uint32_t)GPIOB:
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gpiob_pin_list |= aGpioConfigList[local_loop].pin;
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break;
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case (uint32_t)GPIOC:
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gpioc_pin_list |= aGpioConfigList[local_loop].pin;
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break;
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default:
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break;
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}
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}
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}
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STBY_DebugGpioaPinList = gpioa_pin_list;
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STBY_DebugGpiobPinList = gpiob_pin_list;
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STBY_DebugGpiocPinList = gpioc_pin_list;
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}
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gpio_config.Pull = GPIO_NOPULL;
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gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
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gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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if(gpioa_pin_list != 0)
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{
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gpio_config.Pin = gpioa_pin_list;
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_C2GPIOA_CLK_ENABLE();
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HAL_GPIO_Init(GPIOA, &gpio_config);
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HAL_GPIO_WritePin(GPIOA, gpioa_pin_list, GPIO_PIN_RESET);
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||||
}
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if(gpiob_pin_list != 0)
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{
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gpio_config.Pin = gpiob_pin_list;
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_C2GPIOB_CLK_ENABLE();
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HAL_GPIO_Init(GPIOB, &gpio_config);
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HAL_GPIO_WritePin(GPIOB, gpiob_pin_list, GPIO_PIN_RESET);
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}
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if(gpioc_pin_list != 0)
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||||
{
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||||
gpio_config.Pin = gpioc_pin_list;
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||||
__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_C2GPIOC_CLK_ENABLE();
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HAL_GPIO_Init(GPIOC, &gpio_config);
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||||
HAL_GPIO_WritePin(GPIOC, gpioc_pin_list, GPIO_PIN_RESET);
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||||
}
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||||
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||||
/* USER CODE END APPD_SetCPU2GpioConfig */
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||||
return;
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||||
}
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||||
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||||
static void APPD_BleDtbCfg( void )
|
||||
{
|
||||
/* USER CODE BEGIN APPD_BleDtbCfg */
|
||||
#if (BLE_DTB_CFG != 0)
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||||
GPIO_InitTypeDef gpio_config = {0};
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||||
uint8_t local_loop;
|
||||
uint16_t gpioa_pin_list;
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||||
uint16_t gpiob_pin_list;
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||||
gpioa_pin_list = STBY_DtbGpioaPinList;
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||||
gpiob_pin_list = STBY_DtbGpiobPinList;
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||||
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||||
if(gpioa_pin_list == UINT16_MAX)
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||||
{
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||||
gpioa_pin_list = 0;
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||||
gpiob_pin_list = 0;
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||||
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for(local_loop = 0 ; local_loop < GPIO_NBR_OF_RF_SIGNALS; local_loop++)
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||||
{
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||||
if( aRfConfigList[local_loop].enable != 0)
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||||
{
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||||
switch((uint32_t)aRfConfigList[local_loop].port)
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||||
{
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||||
case (uint32_t)GPIOA:
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gpioa_pin_list |= aRfConfigList[local_loop].pin;
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break;
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case (uint32_t)GPIOB:
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gpiob_pin_list |= aRfConfigList[local_loop].pin;
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break;
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default:
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break;
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||||
}
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}
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||||
}
|
||||
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||||
STBY_DtbGpioaPinList = gpioa_pin_list;
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||||
STBY_DtbGpiobPinList = gpiob_pin_list;
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||||
}
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gpio_config.Pull = GPIO_NOPULL;
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||||
gpio_config.Mode = GPIO_MODE_AF_PP;
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||||
gpio_config.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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||||
gpio_config.Alternate = GPIO_AF6_RF_DTB7;
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||||
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||||
if(gpioa_pin_list != 0)
|
||||
{
|
||||
gpio_config.Pin = gpioa_pin_list;
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_C2GPIOA_CLK_ENABLE();
|
||||
HAL_GPIO_Init(GPIOA, &gpio_config);
|
||||
}
|
||||
|
||||
if(gpiob_pin_list != 0)
|
||||
{
|
||||
gpio_config.Pin = gpiob_pin_list;
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_C2GPIOB_CLK_ENABLE();
|
||||
HAL_GPIO_Init(GPIOB, &gpio_config);
|
||||
}
|
||||
#else
|
||||
STBY_DtbGpioaPinList = 0;
|
||||
STBY_DtbGpiobPinList = 0;
|
||||
#endif
|
||||
|
||||
/* USER CODE END APPD_BleDtbCfg */
|
||||
return;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
*
|
||||
* WRAP FUNCTIONS
|
||||
*
|
||||
*************************************************************/
|
||||
#if(CFG_DEBUG_TRACE != 0)
|
||||
void DbgOutputInit( void )
|
||||
{
|
||||
/* USER CODE BEGIN DbgOutputInit */
|
||||
#ifdef CFG_DEBUG_TRACE_UART
|
||||
if (CFG_DEBUG_TRACE_UART == hw_lpuart1)
|
||||
{
|
||||
#if(CFG_HW_LPUART1_ENABLED == 1)
|
||||
MX_LPUART1_UART_Init();
|
||||
#endif
|
||||
}
|
||||
else if (CFG_DEBUG_TRACE_UART == hw_uart1)
|
||||
{
|
||||
#if(CFG_HW_USART1_ENABLED == 1)
|
||||
MX_USART1_UART_Init();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* USER CODE END DbgOutputInit */
|
||||
return;
|
||||
}
|
||||
|
||||
void DbgOutputTraces( uint8_t *p_data, uint16_t size, void (*cb)(void) )
|
||||
{
|
||||
/* USER CODE BEGIN DbgOutputTraces */
|
||||
//HW_UART_Transmit_DMA(CFG_DEBUG_TRACE_UART, p_data, size, cb);
|
||||
HAL_UART_Transmit(hw_uart1, p_data, size, HAL_MAX_DELAY);
|
||||
|
||||
/* USER CODE END DbgOutputTraces */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
@@ -1,588 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file app_entry.c
|
||||
* @author MCD Application Team
|
||||
* @brief Entry point of the application
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "app_common.h"
|
||||
#include "main.h"
|
||||
#include "app_entry.h"
|
||||
#include "app_ble.h"
|
||||
#include "ble.h"
|
||||
#include "tl.h"
|
||||
#include "stm32_seq.h"
|
||||
#include "shci_tl.h"
|
||||
#include "stm32_lpm.h"
|
||||
#include "app_debug.h"
|
||||
#include "dbg_trace.h"
|
||||
#include "shci.h"
|
||||
#include "otp.h"
|
||||
|
||||
/* Private includes -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
extern RTC_HandleTypeDef hrtc;
|
||||
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC((sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE), 4U))
|
||||
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
|
||||
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
|
||||
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
|
||||
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
|
||||
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private functions prototypes-----------------------------------------------*/
|
||||
static void Config_HSE(void);
|
||||
static void Reset_Device(void);
|
||||
#if (CFG_HW_RESET_BY_FW == 1)
|
||||
static void Reset_IPCC(void);
|
||||
static void Reset_BackupDomain(void);
|
||||
#endif /* CFG_HW_RESET_BY_FW == 1*/
|
||||
static void System_Init(void);
|
||||
static void SystemPower_Config(void);
|
||||
static void appe_Tl_Init(void);
|
||||
static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status);
|
||||
static void APPE_SysUserEvtRx(void * pPayload);
|
||||
static void APPE_SysEvtReadyProcessing(void * pPayload);
|
||||
static void APPE_SysEvtError(void * pPayload);
|
||||
static void Init_Rtc(void);
|
||||
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Functions Definition ------------------------------------------------------*/
|
||||
void MX_APPE_Config(void)
|
||||
{
|
||||
/**
|
||||
* The OPTVERR flag is wrongly set at power on
|
||||
* It shall be cleared before using any HAL_FLASH_xxx() api
|
||||
*/
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
|
||||
|
||||
/**
|
||||
* Reset some configurations so that the system behave in the same way
|
||||
* when either out of nReset or Power On
|
||||
*/
|
||||
Reset_Device();
|
||||
|
||||
/* Configure HSE Tuning */
|
||||
Config_HSE();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void MX_APPE_Init(void)
|
||||
{
|
||||
System_Init(); /**< System initialization */
|
||||
|
||||
SystemPower_Config(); /**< Configure the system Power Mode */
|
||||
|
||||
HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
|
||||
|
||||
/* USER CODE BEGIN APPE_Init_1 */
|
||||
|
||||
/* USER CODE END APPE_Init_1 */
|
||||
appe_Tl_Init(); /* Initialize all transport layers */
|
||||
|
||||
/**
|
||||
* From now, the application is waiting for the ready event (VS_HCI_C2_Ready)
|
||||
* received on the system channel before starting the Stack
|
||||
* This system event is received with APPE_SysUserEvtRx()
|
||||
*/
|
||||
/* USER CODE BEGIN APPE_Init_2 */
|
||||
|
||||
/* USER CODE END APPE_Init_2 */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void Init_Smps(void)
|
||||
{
|
||||
#if (CFG_USE_SMPS != 0)
|
||||
/**
|
||||
* Configure and enable SMPS
|
||||
*
|
||||
* The SMPS configuration is not yet supported by CubeMx
|
||||
* when SMPS output voltage is set to 1.4V, the RF output power is limited to 3.7dBm
|
||||
* the SMPS output voltage shall be increased for higher RF output power
|
||||
*/
|
||||
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
|
||||
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
|
||||
LL_PWR_SMPS_Enable();
|
||||
#endif /* CFG_USE_SMPS != 0 */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void Init_Exti(void)
|
||||
{
|
||||
/* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */
|
||||
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN FD */
|
||||
|
||||
/* USER CODE END FD */
|
||||
|
||||
/*************************************************************
|
||||
*
|
||||
* LOCAL FUNCTIONS
|
||||
*
|
||||
*************************************************************/
|
||||
static void Reset_Device(void)
|
||||
{
|
||||
#if (CFG_HW_RESET_BY_FW == 1)
|
||||
Reset_BackupDomain();
|
||||
|
||||
Reset_IPCC();
|
||||
#endif /* CFG_HW_RESET_BY_FW == 1 */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#if (CFG_HW_RESET_BY_FW == 1)
|
||||
static void Reset_BackupDomain(void)
|
||||
{
|
||||
if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
|
||||
{
|
||||
HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
|
||||
|
||||
/**
|
||||
* Write twice the value to flush the APB-AHB bridge
|
||||
* This bit shall be written in the register before writing the next one
|
||||
*/
|
||||
HAL_PWR_EnableBkUpAccess();
|
||||
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void Reset_IPCC(void)
|
||||
{
|
||||
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
|
||||
|
||||
LL_C1_IPCC_ClearFlag_CHx(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
LL_C2_IPCC_ClearFlag_CHx(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
LL_C1_IPCC_DisableTransmitChannel(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
LL_C2_IPCC_DisableTransmitChannel(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
LL_C1_IPCC_DisableReceiveChannel(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
LL_C2_IPCC_DisableReceiveChannel(
|
||||
IPCC,
|
||||
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
|
||||
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif /* CFG_HW_RESET_BY_FW == 1 */
|
||||
|
||||
static void Config_HSE(void)
|
||||
{
|
||||
OTP_ID0_t * p_otp;
|
||||
|
||||
/**
|
||||
* Read HSE_Tuning from OTP
|
||||
*/
|
||||
p_otp = (OTP_ID0_t *) OTP_Read(0);
|
||||
if (p_otp)
|
||||
{
|
||||
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void System_Init(void)
|
||||
{
|
||||
Init_Smps();
|
||||
|
||||
Init_Exti();
|
||||
|
||||
Init_Rtc();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void Init_Rtc(void)
|
||||
{
|
||||
/* Disable RTC registers write protection */
|
||||
LL_RTC_DisableWriteProtection(RTC);
|
||||
|
||||
LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
|
||||
|
||||
/* Enable RTC registers write protection */
|
||||
LL_RTC_EnableWriteProtection(RTC);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the system for power optimization
|
||||
*
|
||||
* @note This API configures the system to be ready for low power mode
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SystemPower_Config(void)
|
||||
{
|
||||
/**
|
||||
* Select HSI as system clock source after Wake Up from Stop mode
|
||||
*/
|
||||
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
|
||||
|
||||
/* Initialize low power manager */
|
||||
UTIL_LPM_Init();
|
||||
/* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */
|
||||
LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
|
||||
|
||||
#if (CFG_USB_INTERFACE_ENABLE != 0)
|
||||
/**
|
||||
* Enable USB power
|
||||
*/
|
||||
HAL_PWREx_EnableVddUSB();
|
||||
#endif /* CFG_USB_INTERFACE_ENABLE != 0 */
|
||||
/**
|
||||
* Active SRAM retention for standby support
|
||||
*/
|
||||
HAL_PWREx_EnableSRAMRetention();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void appe_Tl_Init(void)
|
||||
{
|
||||
TL_MM_Config_t tl_mm_config;
|
||||
SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
|
||||
/**< Reference table initialization */
|
||||
TL_Init();
|
||||
|
||||
/**< System channel initialization */
|
||||
UTIL_SEQ_RegTask(1<< CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, UTIL_SEQ_RFU, shci_user_evt_proc);
|
||||
SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
|
||||
SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
|
||||
shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
|
||||
|
||||
/**< Memory Manager channel initialization */
|
||||
tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
|
||||
tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
|
||||
tl_mm_config.p_AsynchEvtPool = EvtPool;
|
||||
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
|
||||
TL_MM_Init(&tl_mm_config);
|
||||
|
||||
TL_Enable();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status)
|
||||
{
|
||||
UNUSED(status);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* The type of the payload for a system user event is tSHCI_UserEvtRxParam
|
||||
* When the system event is both :
|
||||
* - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
|
||||
* - reported by the FUS (sysevt_ready_rsp == FUS_FW_RUNNING)
|
||||
* The buffer shall not be released
|
||||
* (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable)
|
||||
* When the status is not filled, the buffer is released by default
|
||||
*/
|
||||
static void APPE_SysUserEvtRx(void * pPayload)
|
||||
{
|
||||
TL_AsynchEvt_t *p_sys_event;
|
||||
WirelessFwInfo_t WirelessInfo;
|
||||
|
||||
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
||||
|
||||
switch(p_sys_event->subevtcode)
|
||||
{
|
||||
case SHCI_SUB_EVT_CODE_READY:
|
||||
/* Read the firmware version of both the wireless firmware and the FUS */
|
||||
SHCI_GetWirelessFwInfo(&WirelessInfo);
|
||||
APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub);
|
||||
APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType);
|
||||
APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub);
|
||||
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r");
|
||||
APPE_SysEvtReadyProcessing(pPayload);
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_ERROR_NOTIF:
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r");
|
||||
APPE_SysEvtError(pPayload);
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE:
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE -- BLE NVM RAM HAS BEEN UPDATED BY CPU2 \n");
|
||||
APP_DBG_MSG(" - StartAddress = %lx , Size = %ld\n",
|
||||
((SHCI_C2_BleNvmRamUpdate_Evt_t*)p_sys_event->payload)->StartAddress,
|
||||
((SHCI_C2_BleNvmRamUpdate_Evt_t*)p_sys_event->payload)->Size);
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_NVM_START_WRITE:
|
||||
APP_DBG_MSG("==>> SHCI_SUB_EVT_NVM_START_WRITE : NumberOfWords = %ld\n",
|
||||
((SHCI_C2_NvmStartWrite_Evt_t*)p_sys_event->payload)->NumberOfWords);
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_NVM_END_WRITE:
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_WRITE\n\r");
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_NVM_START_ERASE:
|
||||
APP_DBG_MSG("==>>SHCI_SUB_EVT_NVM_START_ERASE : NumberOfSectors = %ld\n",
|
||||
((SHCI_C2_NvmStartErase_Evt_t*)p_sys_event->payload)->NumberOfSectors);
|
||||
break;
|
||||
|
||||
case SHCI_SUB_EVT_NVM_END_ERASE:
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Notify a system error coming from the M0 firmware
|
||||
* @param ErrorCode : errorCode detected by the M0 firmware
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void APPE_SysEvtError(void * pPayload)
|
||||
{
|
||||
TL_AsynchEvt_t *p_sys_event;
|
||||
SCHI_SystemErrCode_t *p_sys_error_code;
|
||||
|
||||
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
||||
p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload;
|
||||
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON %x \n\r",(*p_sys_error_code));
|
||||
|
||||
if ((*p_sys_error_code) == ERR_BLE_INIT)
|
||||
{
|
||||
/* Error during BLE stack initialization */
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - ERR_BLE_INIT \n");
|
||||
}
|
||||
else
|
||||
{
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n");
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void APPE_SysEvtReadyProcessing(void * pPayload)
|
||||
{
|
||||
TL_AsynchEvt_t *p_sys_event;
|
||||
SHCI_C2_Ready_Evt_t *p_sys_ready_event;
|
||||
|
||||
SHCI_C2_CONFIG_Cmd_Param_t config_param = {0};
|
||||
uint32_t RevisionID=0;
|
||||
uint32_t DeviceID=0;
|
||||
|
||||
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
||||
p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload;
|
||||
|
||||
if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING)
|
||||
{
|
||||
/**
|
||||
* The wireless firmware is running on the CPU2
|
||||
*/
|
||||
APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n");
|
||||
|
||||
/* Traces channel initialization */
|
||||
APPD_EnableCPU2();
|
||||
|
||||
/* Enable all events Notification */
|
||||
config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE;
|
||||
config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE
|
||||
+ SHCI_C2_CONFIG_EVTMASK1_BIT6_NVM_END_ERASE_ENABLE;
|
||||
|
||||
/* Read revision identifier */
|
||||
/**
|
||||
* @brief Return the device revision identifier
|
||||
* @note This field indicates the revision of the device.
|
||||
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
||||
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
*/
|
||||
RevisionID = LL_DBGMCU_GetRevisionID();
|
||||
|
||||
APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID);
|
||||
|
||||
config_param.RevisionID = (uint16_t)RevisionID;
|
||||
|
||||
DeviceID = LL_DBGMCU_GetDeviceID();
|
||||
APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID);
|
||||
config_param.DeviceID = (uint16_t)DeviceID;
|
||||
(void)SHCI_C2_Config(&config_param);
|
||||
|
||||
APP_BLE_Init();
|
||||
UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
|
||||
}
|
||||
else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING)
|
||||
{
|
||||
/**
|
||||
* The FUS firmware is running on the CPU2
|
||||
* In the scope of this application, there should be no case when we get here
|
||||
*/
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - FUS_FW_RUNNING \n\r");
|
||||
|
||||
/* The packet shall not be released as this is not supported by the FUS */
|
||||
((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable;
|
||||
}
|
||||
else
|
||||
{
|
||||
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
|
||||
|
||||
/* USER CODE END FD_LOCAL_FUNCTIONS */
|
||||
|
||||
/*************************************************************
|
||||
*
|
||||
* WRAP FUNCTIONS
|
||||
*
|
||||
*************************************************************/
|
||||
void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += HAL_GetTickFreq();
|
||||
}
|
||||
|
||||
while ((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
/************************************************************************************
|
||||
* ENTER SLEEP MODE
|
||||
***********************************************************************************/
|
||||
LL_LPM_EnableSleep(); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
|
||||
/**
|
||||
* This option is used to ensure that store operations are completed
|
||||
*/
|
||||
#if defined (__CC_ARM) || defined (__ARMCC_VERSION)
|
||||
__force_stores();
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
__WFI();
|
||||
}
|
||||
}
|
||||
|
||||
void MX_APPE_Process(void)
|
||||
{
|
||||
/* USER CODE BEGIN MX_APPE_Process_1 */
|
||||
|
||||
/* USER CODE END MX_APPE_Process_1 */
|
||||
UTIL_SEQ_Run(UTIL_SEQ_DEFAULT);
|
||||
/* USER CODE BEGIN MX_APPE_Process_2 */
|
||||
|
||||
/* USER CODE END MX_APPE_Process_2 */
|
||||
}
|
||||
|
||||
void UTIL_SEQ_Idle(void)
|
||||
{
|
||||
#if (CFG_LPM_SUPPORTED == 1)
|
||||
UTIL_LPM_EnterLowPower();
|
||||
#endif /* CFG_LPM_SUPPORTED == 1 */
|
||||
return;
|
||||
}
|
||||
|
||||
void shci_notify_asynch_evt(void* pdata)
|
||||
{
|
||||
UTIL_SEQ_SetTask(1<<CFG_TASK_SYSTEM_HCI_ASYNCH_EVT_ID, CFG_SCH_PRIO_0);
|
||||
return;
|
||||
}
|
||||
|
||||
void shci_cmd_resp_release(uint32_t flag)
|
||||
{
|
||||
UTIL_SEQ_SetEvt(1<< CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID);
|
||||
return;
|
||||
}
|
||||
|
||||
void shci_cmd_resp_wait(uint32_t timeout)
|
||||
{
|
||||
UTIL_SEQ_WaitEvt(1<< CFG_IDLEEVT_SYSTEM_HCI_CMD_EVT_RSP_ID);
|
||||
return;
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
|
||||
|
||||
/* USER CODE END FD_WRAP_FUNCTIONS */
|
||||
@@ -1,59 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file dma.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of all the requested memory to memory DMA transfers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "dma.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Configure DMA */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/**
|
||||
* Enable DMA controller clock
|
||||
*/
|
||||
void MX_DMA_Init(void)
|
||||
{
|
||||
|
||||
/* DMA controller clock enable */
|
||||
__HAL_RCC_DMAMUX1_CLK_ENABLE();
|
||||
__HAL_RCC_DMA1_CLK_ENABLE();
|
||||
|
||||
/* DMA interrupt init */
|
||||
/* DMA1_Channel1_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
||||
/* DMA1_Channel2_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
|
||||
@@ -1,69 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file gpio.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of all used GPIO pins.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "gpio.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Configure GPIO */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/** Configure pins
|
||||
PA8 ------> RCC_MCO
|
||||
*/
|
||||
void MX_GPIO_Init(void)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(GPIOA, LED4_Pin|LED5_Pin, GPIO_PIN_RESET);
|
||||
|
||||
/*Configure GPIO pin : PA8 */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pins : LED4_Pin LED5_Pin */
|
||||
GPIO_InitStruct.Pin = LED4_Pin|LED5_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
@@ -1,888 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hw_timerserver.c
|
||||
* @author MCD Application Team
|
||||
* @brief Hardware timerserver source file for STM32WPAN Middleware.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "app_common.h"
|
||||
#include "hw_conf.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
typedef enum
|
||||
{
|
||||
TimerID_Free,
|
||||
TimerID_Created,
|
||||
TimerID_Running
|
||||
}TimerIDStatus_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SSR_Read_Requested,
|
||||
SSR_Read_Not_Requested
|
||||
}RequestReadSSR_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
WakeupTimerValue_Overpassed,
|
||||
WakeupTimerValue_LargeEnough
|
||||
}WakeupTimerLimitation_Status_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
HW_TS_pTimerCb_t pTimerCallBack;
|
||||
uint32_t CounterInit;
|
||||
uint32_t CountLeft;
|
||||
TimerIDStatus_t TimerIDStatus;
|
||||
HW_TS_Mode_t TimerMode;
|
||||
uint32_t TimerProcessID;
|
||||
uint8_t PreviousID;
|
||||
uint8_t NextID;
|
||||
}TimerContext_t;
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
#define SSR_FORBIDDEN_VALUE 0xFFFFFFFF
|
||||
#define TIMER_LIST_EMPTY 0xFFFF
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* START of Section TIMERSERVER_CONTEXT
|
||||
*/
|
||||
|
||||
static volatile TimerContext_t aTimerContext[CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER];
|
||||
static volatile uint8_t CurrentRunningTimerID;
|
||||
static volatile uint8_t PreviousRunningTimerID;
|
||||
static volatile uint32_t SSRValueOnLastSetup;
|
||||
static volatile WakeupTimerLimitation_Status_t WakeupTimerLimitation;
|
||||
|
||||
/**
|
||||
* END of Section TIMERSERVER_CONTEXT
|
||||
*/
|
||||
|
||||
static uint8_t WakeupTimerDivider;
|
||||
static uint8_t AsynchPrescalerUserConfig;
|
||||
static uint16_t SynchPrescalerUserConfig;
|
||||
static volatile uint16_t MaxWakeupTimerSetup;
|
||||
|
||||
/* Global variables ----------------------------------------------------------*/
|
||||
extern RTC_HandleTypeDef hrtc;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void RestartWakeupCounter(uint16_t Value);
|
||||
static uint16_t ReturnTimeElapsed(void);
|
||||
static void RescheduleTimerList(void);
|
||||
static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR);
|
||||
static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID);
|
||||
static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID);
|
||||
static uint16_t linkTimer(uint8_t TimerID);
|
||||
static uint32_t ReadRtcSsrValue(void);
|
||||
|
||||
__weak void HW_TS_RTC_CountUpdated_AppNot(void);
|
||||
|
||||
/* Functions Definition ------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Read the RTC_SSR value
|
||||
* As described in the reference manual, the RTC_SSR shall be read twice to ensure
|
||||
* reliability of the value
|
||||
* @param None
|
||||
* @retval SSR value read
|
||||
*/
|
||||
static uint32_t ReadRtcSsrValue(void)
|
||||
{
|
||||
uint32_t first_read;
|
||||
uint32_t second_read;
|
||||
|
||||
first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
||||
|
||||
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
||||
|
||||
while(first_read != second_read)
|
||||
{
|
||||
first_read = second_read;
|
||||
|
||||
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
||||
}
|
||||
|
||||
return second_read;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Insert a Timer in the list after the Timer ID specified
|
||||
* @param TimerID: The ID of the Timer
|
||||
* @param RefTimerID: The ID of the Timer to be linked after
|
||||
* @retval None
|
||||
*/
|
||||
static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
|
||||
{
|
||||
uint8_t next_id;
|
||||
|
||||
next_id = aTimerContext[RefTimerID].NextID;
|
||||
|
||||
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
aTimerContext[next_id].PreviousID = TimerID;
|
||||
}
|
||||
aTimerContext[TimerID].NextID = next_id;
|
||||
aTimerContext[TimerID].PreviousID = RefTimerID ;
|
||||
aTimerContext[RefTimerID].NextID = TimerID;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Insert a Timer in the list before the ID specified
|
||||
* @param TimerID: The ID of the Timer
|
||||
* @param RefTimerID: The ID of the Timer to be linked before
|
||||
* @retval None
|
||||
*/
|
||||
static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
|
||||
{
|
||||
uint8_t previous_id;
|
||||
|
||||
if(RefTimerID != CurrentRunningTimerID)
|
||||
{
|
||||
previous_id = aTimerContext[RefTimerID].PreviousID;
|
||||
|
||||
aTimerContext[previous_id].NextID = TimerID;
|
||||
aTimerContext[TimerID].NextID = RefTimerID;
|
||||
aTimerContext[TimerID].PreviousID = previous_id ;
|
||||
aTimerContext[RefTimerID].PreviousID = TimerID;
|
||||
}
|
||||
else
|
||||
{
|
||||
aTimerContext[TimerID].NextID = RefTimerID;
|
||||
aTimerContext[RefTimerID].PreviousID = TimerID;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Insert a Timer in the list
|
||||
* @param TimerID: The ID of the Timer
|
||||
* @retval None
|
||||
*/
|
||||
static uint16_t linkTimer(uint8_t TimerID)
|
||||
{
|
||||
uint32_t time_left;
|
||||
uint16_t time_elapsed;
|
||||
uint8_t timer_id_lookup;
|
||||
uint8_t next_id;
|
||||
|
||||
if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
/**
|
||||
* No timer in the list
|
||||
*/
|
||||
PreviousRunningTimerID = CurrentRunningTimerID;
|
||||
CurrentRunningTimerID = TimerID;
|
||||
aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
|
||||
|
||||
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
||||
time_elapsed = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
time_elapsed = ReturnTimeElapsed();
|
||||
|
||||
/**
|
||||
* update count of the timer to be linked
|
||||
*/
|
||||
aTimerContext[TimerID].CountLeft += time_elapsed;
|
||||
time_left = aTimerContext[TimerID].CountLeft;
|
||||
|
||||
/**
|
||||
* Search for index where the new timer shall be linked
|
||||
*/
|
||||
if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
|
||||
{
|
||||
/**
|
||||
* Search for the ID after the first one
|
||||
*/
|
||||
timer_id_lookup = CurrentRunningTimerID;
|
||||
next_id = aTimerContext[timer_id_lookup].NextID;
|
||||
while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
|
||||
{
|
||||
timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
|
||||
next_id = aTimerContext[timer_id_lookup].NextID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Link after the ID
|
||||
*/
|
||||
LinkTimerAfter(TimerID, timer_id_lookup);
|
||||
}
|
||||
else
|
||||
{
|
||||
/**
|
||||
* Link before the first ID
|
||||
*/
|
||||
LinkTimerBefore(TimerID, CurrentRunningTimerID);
|
||||
PreviousRunningTimerID = CurrentRunningTimerID;
|
||||
CurrentRunningTimerID = TimerID;
|
||||
}
|
||||
}
|
||||
|
||||
return time_elapsed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Remove a Timer from the list
|
||||
* @param TimerID: The ID of the Timer
|
||||
* @param RequestReadSSR: Request to read the SSR register or not
|
||||
* @retval None
|
||||
*/
|
||||
static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
|
||||
{
|
||||
uint8_t previous_id;
|
||||
uint8_t next_id;
|
||||
|
||||
if(TimerID == CurrentRunningTimerID)
|
||||
{
|
||||
PreviousRunningTimerID = CurrentRunningTimerID;
|
||||
CurrentRunningTimerID = aTimerContext[TimerID].NextID;
|
||||
}
|
||||
else
|
||||
{
|
||||
previous_id = aTimerContext[TimerID].PreviousID;
|
||||
next_id = aTimerContext[TimerID].NextID;
|
||||
|
||||
aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
|
||||
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Timer is out of the list
|
||||
*/
|
||||
aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
|
||||
|
||||
if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
|
||||
{
|
||||
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the number of ticks counted by the wakeuptimer since it has been started
|
||||
* @note The API is reading the SSR register to get how many ticks have been counted
|
||||
* since the time the timer has been started
|
||||
* @param None
|
||||
* @retval Time expired in Ticks
|
||||
*/
|
||||
static uint16_t ReturnTimeElapsed(void)
|
||||
{
|
||||
uint32_t return_value;
|
||||
uint32_t wrap_counter;
|
||||
|
||||
if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
|
||||
{
|
||||
return_value = ReadRtcSsrValue(); /**< Read SSR register first */
|
||||
|
||||
if (SSRValueOnLastSetup >= return_value)
|
||||
{
|
||||
return_value = SSRValueOnLastSetup - return_value;
|
||||
}
|
||||
else
|
||||
{
|
||||
wrap_counter = SynchPrescalerUserConfig - return_value;
|
||||
return_value = SSRValueOnLastSetup + wrap_counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* At this stage, ReturnValue holds the number of ticks counted by SSR
|
||||
* Need to translate in number of ticks counted by the Wakeuptimer
|
||||
*/
|
||||
return_value = return_value*AsynchPrescalerUserConfig;
|
||||
return_value = return_value >> WakeupTimerDivider;
|
||||
}
|
||||
else
|
||||
{
|
||||
return_value = 0;
|
||||
}
|
||||
|
||||
return (uint16_t)return_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wakeup counter
|
||||
* @note The API is writing the counter value so that the value is decreased by one to cope with the fact
|
||||
* the interrupt is generated with 1 extra clock cycle (See RefManuel)
|
||||
* It assumes all condition are met to be allowed to write the wakeup counter
|
||||
* @param Value: Value to be written in the counter
|
||||
* @retval None
|
||||
*/
|
||||
static void RestartWakeupCounter(uint16_t Value)
|
||||
{
|
||||
/**
|
||||
* The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
|
||||
* FLAG when the new value will have to be written
|
||||
* __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
|
||||
*/
|
||||
|
||||
if(Value == 0)
|
||||
{
|
||||
SSRValueOnLastSetup = ReadRtcSsrValue();
|
||||
|
||||
/**
|
||||
* Simulate that the Timer expired
|
||||
*/
|
||||
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
|
||||
}
|
||||
else
|
||||
{
|
||||
if((Value > 1) ||(WakeupTimerDivider != 1))
|
||||
{
|
||||
Value -= 1;
|
||||
}
|
||||
|
||||
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
||||
|
||||
/**
|
||||
* make sure to clear the flags after checking the WUTWF.
|
||||
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
|
||||
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
|
||||
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
|
||||
* due to the autoreload feature
|
||||
*/
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
||||
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
||||
|
||||
MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
|
||||
|
||||
/**
|
||||
* Update the value here after the WUTWF polling that may take some time
|
||||
*/
|
||||
SSRValueOnLastSetup = ReadRtcSsrValue();
|
||||
|
||||
__HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */
|
||||
|
||||
HW_TS_RTC_CountUpdated_AppNot();
|
||||
}
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reschedule the list of timer
|
||||
* @note 1) Update the count left for each timer in the list
|
||||
* 2) Setup the wakeuptimer
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void RescheduleTimerList(void)
|
||||
{
|
||||
uint8_t localTimerID;
|
||||
uint32_t timecountleft;
|
||||
uint16_t wakeup_timer_value;
|
||||
uint16_t time_elapsed;
|
||||
|
||||
/**
|
||||
* The wakeuptimer is disabled now to reduce the time to poll the WUTWF
|
||||
* FLAG when the new value will have to be written
|
||||
*/
|
||||
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
|
||||
{
|
||||
/**
|
||||
* Wait for the flag to be back to 0 when the wakeup timer is enabled
|
||||
*/
|
||||
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
|
||||
}
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
||||
|
||||
localTimerID = CurrentRunningTimerID;
|
||||
|
||||
/**
|
||||
* Calculate what will be the value to write in the wakeuptimer
|
||||
*/
|
||||
timecountleft = aTimerContext[localTimerID].CountLeft;
|
||||
|
||||
/**
|
||||
* Read how much has been counted
|
||||
*/
|
||||
time_elapsed = ReturnTimeElapsed();
|
||||
|
||||
if(timecountleft < time_elapsed )
|
||||
{
|
||||
/**
|
||||
* There is no tick left to count
|
||||
*/
|
||||
wakeup_timer_value = 0;
|
||||
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
|
||||
{
|
||||
/**
|
||||
* The number of tick left is greater than the Wakeuptimer maximum value
|
||||
*/
|
||||
wakeup_timer_value = MaxWakeupTimerSetup;
|
||||
|
||||
WakeupTimerLimitation = WakeupTimerValue_Overpassed;
|
||||
}
|
||||
else
|
||||
{
|
||||
wakeup_timer_value = timecountleft - time_elapsed;
|
||||
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* update ticks left to be counted for each timer
|
||||
*/
|
||||
while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
if (aTimerContext[localTimerID].CountLeft < time_elapsed)
|
||||
{
|
||||
aTimerContext[localTimerID].CountLeft = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
aTimerContext[localTimerID].CountLeft -= time_elapsed;
|
||||
}
|
||||
localTimerID = aTimerContext[localTimerID].NextID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write next count
|
||||
*/
|
||||
RestartWakeupCounter(wakeup_timer_value);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/* Public functions ----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* For all public interface except that may need write access to the RTC, the RTC
|
||||
* shall be unlock at the beginning and locked at the output
|
||||
* In order to ease maintainability, the unlock is done at the top and the lock at then end
|
||||
* in case some new implementation is coming in the future
|
||||
*/
|
||||
|
||||
void HW_TS_RTC_Wakeup_Handler(void)
|
||||
{
|
||||
HW_TS_pTimerCb_t ptimer_callback;
|
||||
uint32_t timer_process_id;
|
||||
uint8_t local_current_running_timer_id;
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
uint32_t primask_bit;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
||||
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
||||
#endif
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
|
||||
/**
|
||||
* Disable the Wakeup Timer
|
||||
* This may speed up a bit the processing to wait the timer to be disabled
|
||||
* The timer is still counting 2 RTCCLK
|
||||
*/
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
|
||||
|
||||
local_current_running_timer_id = CurrentRunningTimerID;
|
||||
|
||||
if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
|
||||
{
|
||||
ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
|
||||
timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
|
||||
|
||||
/**
|
||||
* It should be good to check whether the TimeElapsed is greater or not than the tick left to be counted
|
||||
* However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
|
||||
* to be left whereas the count is over
|
||||
* A more secure implementation has been done with a flag to state whereas the full count has been written
|
||||
* in the wakeuptimer or not
|
||||
*/
|
||||
if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
|
||||
{
|
||||
if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
|
||||
{
|
||||
UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
HW_TS_Stop(local_current_running_timer_id);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
}
|
||||
|
||||
HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
|
||||
}
|
||||
else
|
||||
{
|
||||
RescheduleTimerList();
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/**
|
||||
* We should never end up in this case
|
||||
* However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
|
||||
* We could just clean the interrupt flag and get out from this unexpected interrupt
|
||||
*/
|
||||
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
||||
|
||||
/**
|
||||
* make sure to clear the flags after checking the WUTWF.
|
||||
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
|
||||
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
|
||||
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
|
||||
* due to the autoreload feature
|
||||
*/
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc)
|
||||
{
|
||||
uint8_t loop;
|
||||
uint32_t localmaxwakeuptimersetup;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
|
||||
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
||||
|
||||
/**
|
||||
* Readout the user config
|
||||
*/
|
||||
WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
|
||||
|
||||
AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
|
||||
|
||||
SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
|
||||
|
||||
/**
|
||||
* Margin is taken to avoid wrong calculation when the wrap around is there and some
|
||||
* application interrupts may have delayed the reading
|
||||
*/
|
||||
localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
|
||||
|
||||
if(localmaxwakeuptimersetup >= 0xFFFF)
|
||||
{
|
||||
MaxWakeupTimerSetup = 0xFFFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure EXTI module
|
||||
*/
|
||||
LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
|
||||
LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
|
||||
|
||||
if(TimerInitMode == hw_ts_InitMode_Full)
|
||||
{
|
||||
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
||||
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
||||
|
||||
/**
|
||||
* Initialize the timer server
|
||||
*/
|
||||
for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
|
||||
{
|
||||
aTimerContext[loop].TimerIDStatus = TimerID_Free;
|
||||
}
|
||||
|
||||
CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */
|
||||
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
||||
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
||||
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */
|
||||
}
|
||||
else
|
||||
{
|
||||
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET)
|
||||
{
|
||||
/**
|
||||
* Simulate that the Timer expired
|
||||
*/
|
||||
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
||||
|
||||
HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */
|
||||
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
HW_TS_ReturnStatus_t HW_TS_Create(uint32_t TimerProcessID, uint8_t *pTimerId, HW_TS_Mode_t TimerMode, HW_TS_pTimerCb_t pftimeout_handler)
|
||||
{
|
||||
HW_TS_ReturnStatus_t localreturnstatus;
|
||||
uint8_t loop = 0;
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
uint32_t primask_bit;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
||||
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
||||
#endif
|
||||
|
||||
while((loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[loop].TimerIDStatus != TimerID_Free))
|
||||
{
|
||||
loop++;
|
||||
}
|
||||
|
||||
if(loop != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
aTimerContext[loop].TimerIDStatus = TimerID_Created;
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
|
||||
aTimerContext[loop].TimerProcessID = TimerProcessID;
|
||||
aTimerContext[loop].TimerMode = TimerMode;
|
||||
aTimerContext[loop].pTimerCallBack = pftimeout_handler;
|
||||
*pTimerId = loop;
|
||||
|
||||
localreturnstatus = hw_ts_Successful;
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
|
||||
localreturnstatus = hw_ts_Failed;
|
||||
}
|
||||
|
||||
return(localreturnstatus);
|
||||
}
|
||||
|
||||
void HW_TS_Delete(uint8_t timer_id)
|
||||
{
|
||||
HW_TS_Stop(timer_id);
|
||||
|
||||
aTimerContext[timer_id].TimerIDStatus = TimerID_Free; /**< release ID */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HW_TS_Stop(uint8_t timer_id)
|
||||
{
|
||||
uint8_t localcurrentrunningtimerid;
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
uint32_t primask_bit;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
||||
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
||||
#endif
|
||||
|
||||
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
|
||||
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
|
||||
{
|
||||
UnlinkTimer(timer_id, SSR_Read_Requested);
|
||||
localcurrentrunningtimerid = CurrentRunningTimerID;
|
||||
|
||||
if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
||||
{
|
||||
/**
|
||||
* List is empty
|
||||
*/
|
||||
|
||||
/**
|
||||
* Disable the timer
|
||||
*/
|
||||
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
|
||||
{
|
||||
/**
|
||||
* Wait for the flag to be back to 0 when the wakeup timer is enabled
|
||||
*/
|
||||
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
|
||||
}
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
||||
|
||||
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
||||
|
||||
/**
|
||||
* make sure to clear the flags after checking the WUTWF.
|
||||
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
|
||||
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
|
||||
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
|
||||
* due to the autoreload feature
|
||||
*/
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
||||
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
||||
}
|
||||
else if(PreviousRunningTimerID != localcurrentrunningtimerid)
|
||||
{
|
||||
RescheduleTimerList();
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
||||
|
||||
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
|
||||
{
|
||||
uint16_t time_elapsed;
|
||||
uint8_t localcurrentrunningtimerid;
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
uint32_t primask_bit;
|
||||
#endif
|
||||
|
||||
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
|
||||
{
|
||||
HW_TS_Stop( timer_id );
|
||||
}
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
||||
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
||||
#endif
|
||||
|
||||
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
||||
|
||||
aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
|
||||
|
||||
aTimerContext[timer_id].CountLeft = timeout_ticks;
|
||||
aTimerContext[timer_id].CounterInit = timeout_ticks;
|
||||
|
||||
time_elapsed = linkTimer(timer_id);
|
||||
|
||||
localcurrentrunningtimerid = CurrentRunningTimerID;
|
||||
|
||||
if(PreviousRunningTimerID != localcurrentrunningtimerid)
|
||||
{
|
||||
RescheduleTimerList();
|
||||
}
|
||||
else
|
||||
{
|
||||
aTimerContext[timer_id].CountLeft -= time_elapsed;
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
||||
|
||||
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
||||
|
||||
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
uint16_t HW_TS_RTC_ReadLeftTicksToCount(void)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
uint16_t return_value, auro_reload_value, elapsed_time_value;
|
||||
|
||||
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
||||
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
||||
|
||||
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
|
||||
{
|
||||
auro_reload_value = (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
|
||||
|
||||
elapsed_time_value = ReturnTimeElapsed();
|
||||
|
||||
if(auro_reload_value > elapsed_time_value)
|
||||
{
|
||||
return_value = auro_reload_value - elapsed_time_value;
|
||||
}
|
||||
else
|
||||
{
|
||||
return_value = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return_value = TIMER_LIST_EMPTY;
|
||||
}
|
||||
|
||||
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
||||
|
||||
return (return_value);
|
||||
}
|
||||
|
||||
__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
|
||||
{
|
||||
pTimerCallBack();
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -1,317 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Src/hw_uart.c
|
||||
* @author MCD Application Team
|
||||
* @brief HW UART source file for STM32WPAN Middleware.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "app_common.h"
|
||||
#include "hw_conf.h"
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
extern UART_HandleTypeDef hlpuart1;
|
||||
#endif
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
extern UART_HandleTypeDef huart1;
|
||||
#endif
|
||||
|
||||
/* Macros --------------------------------------------------------------------*/
|
||||
#define HW_UART_RX_IT(__HANDLE__, __USART_BASE__) \
|
||||
do{ \
|
||||
HW_##__HANDLE__##RxCb = cb; \
|
||||
(__HANDLE__).Instance = (__USART_BASE__); \
|
||||
HAL_UART_Receive_IT(&(__HANDLE__), p_data, size); \
|
||||
} while(0)
|
||||
|
||||
#define HW_UART_TX_IT(__HANDLE__, __USART_BASE__) \
|
||||
do{ \
|
||||
HW_##__HANDLE__##TxCb = cb; \
|
||||
(__HANDLE__).Instance = (__USART_BASE__); \
|
||||
HAL_UART_Transmit_IT(&(__HANDLE__), p_data, size); \
|
||||
} while(0)
|
||||
|
||||
#define HW_UART_TX(__HANDLE__, __USART_BASE__) \
|
||||
do{ \
|
||||
(__HANDLE__).Instance = (__USART_BASE__); \
|
||||
hal_status = HAL_UART_Transmit(&(__HANDLE__), p_data, size, timeout); \
|
||||
} while(0)
|
||||
|
||||
/* Variables -----------------------------------------------------------------*/
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
|
||||
DMA_HandleTypeDef HW_hdma_huart1_tx ={0};
|
||||
#endif
|
||||
void (*HW_huart1RxCb)(void);
|
||||
void (*HW_huart1TxCb)(void);
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
|
||||
DMA_HandleTypeDef HW_hdma_hlpuart1_tx ={0};
|
||||
#endif
|
||||
void (*HW_hlpuart1RxCb)(void);
|
||||
void (*HW_hlpuart1TxCb)(void);
|
||||
#endif
|
||||
|
||||
void HW_UART_Receive_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
|
||||
{
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case hw_uart1:
|
||||
HW_UART_RX_IT(huart1, USART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case hw_lpuart1:
|
||||
HW_UART_RX_IT(hlpuart1, LPUART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HW_UART_Transmit_IT(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
|
||||
{
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case hw_uart1:
|
||||
HW_UART_TX_IT(huart1, USART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case hw_lpuart1:
|
||||
HW_UART_TX_IT(hlpuart1, LPUART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
hw_status_t HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, uint32_t timeout)
|
||||
{
|
||||
HAL_StatusTypeDef hal_status = HAL_OK;
|
||||
hw_status_t hw_status = hw_uart_ok;
|
||||
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case hw_uart1:
|
||||
HW_UART_TX(huart1, USART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case hw_lpuart1:
|
||||
HW_UART_TX(hlpuart1, LPUART1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (hal_status)
|
||||
{
|
||||
case HAL_OK:
|
||||
hw_status = hw_uart_ok;
|
||||
break;
|
||||
|
||||
case HAL_ERROR:
|
||||
hw_status = hw_uart_error;
|
||||
break;
|
||||
|
||||
case HAL_BUSY:
|
||||
hw_status = hw_uart_busy;
|
||||
break;
|
||||
|
||||
case HAL_TIMEOUT:
|
||||
hw_status = hw_uart_to;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return hw_status;
|
||||
}
|
||||
|
||||
hw_status_t HW_UART_Transmit_DMA(hw_uart_id_t hw_uart_id, uint8_t *p_data, uint16_t size, void (*cb)(void))
|
||||
{
|
||||
HAL_StatusTypeDef hal_status = HAL_OK;
|
||||
hw_status_t hw_status = hw_uart_ok;
|
||||
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case hw_uart1:
|
||||
HW_huart1TxCb = cb;
|
||||
huart1.Instance = USART1;
|
||||
hal_status = HAL_UART_Transmit_DMA(&huart1, p_data, size);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case hw_lpuart1:
|
||||
HW_hlpuart1TxCb = cb;
|
||||
hlpuart1.Instance = LPUART1;
|
||||
hal_status = HAL_UART_Transmit_DMA(&hlpuart1, p_data, size);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (hal_status)
|
||||
{
|
||||
case HAL_OK:
|
||||
hw_status = hw_uart_ok;
|
||||
break;
|
||||
|
||||
case HAL_ERROR:
|
||||
hw_status = hw_uart_error;
|
||||
break;
|
||||
|
||||
case HAL_BUSY:
|
||||
hw_status = hw_uart_busy;
|
||||
break;
|
||||
|
||||
case HAL_TIMEOUT:
|
||||
hw_status = hw_uart_to;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return hw_status;
|
||||
}
|
||||
|
||||
void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id)
|
||||
{
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case hw_uart1:
|
||||
HAL_UART_IRQHandler(&huart1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case hw_lpuart1:
|
||||
HAL_UART_IRQHandler(&hlpuart1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id)
|
||||
{
|
||||
switch (hw_uart_id)
|
||||
{
|
||||
#if (CFG_HW_USART1_DMA_TX_SUPPORTED == 1)
|
||||
case hw_uart1:
|
||||
HAL_DMA_IRQHandler(huart1.hdmatx);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_DMA_TX_SUPPORTED == 1)
|
||||
case hw_lpuart1:
|
||||
HAL_DMA_IRQHandler(hlpuart1.hdmatx);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
switch ((uint32_t)huart->Instance)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case (uint32_t)USART1:
|
||||
if(HW_huart1RxCb)
|
||||
{
|
||||
HW_huart1RxCb();
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case (uint32_t)LPUART1:
|
||||
if(HW_hlpuart1RxCb)
|
||||
{
|
||||
HW_hlpuart1RxCb();
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
switch ((uint32_t)huart->Instance)
|
||||
{
|
||||
#if (CFG_HW_USART1_ENABLED == 1)
|
||||
case (uint32_t)USART1:
|
||||
if(HW_huart1TxCb)
|
||||
{
|
||||
HW_huart1TxCb();
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (CFG_HW_LPUART1_ENABLED == 1)
|
||||
case (uint32_t)LPUART1:
|
||||
if(HW_hlpuart1TxCb)
|
||||
{
|
||||
HW_hlpuart1TxCb();
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -1,96 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file ipcc.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the IPCC instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "ipcc.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
IPCC_HandleTypeDef hipcc;
|
||||
|
||||
/* IPCC init function */
|
||||
void MX_IPCC_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN IPCC_Init 0 */
|
||||
|
||||
/* USER CODE END IPCC_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN IPCC_Init 1 */
|
||||
|
||||
/* USER CODE END IPCC_Init 1 */
|
||||
hipcc.Instance = IPCC;
|
||||
if (HAL_IPCC_Init(&hipcc) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN IPCC_Init 2 */
|
||||
|
||||
/* USER CODE END IPCC_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_IPCC_MspInit(IPCC_HandleTypeDef* ipccHandle)
|
||||
{
|
||||
|
||||
if(ipccHandle->Instance==IPCC)
|
||||
{
|
||||
/* USER CODE BEGIN IPCC_MspInit 0 */
|
||||
|
||||
/* USER CODE END IPCC_MspInit 0 */
|
||||
/* IPCC clock enable */
|
||||
__HAL_RCC_IPCC_CLK_ENABLE();
|
||||
|
||||
/* IPCC interrupt Init */
|
||||
HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
|
||||
HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
|
||||
/* USER CODE BEGIN IPCC_MspInit 1 */
|
||||
|
||||
/* USER CODE END IPCC_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef* ipccHandle)
|
||||
{
|
||||
|
||||
if(ipccHandle->Instance==IPCC)
|
||||
{
|
||||
/* USER CODE BEGIN IPCC_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END IPCC_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_IPCC_CLK_DISABLE();
|
||||
|
||||
/* IPCC interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(IPCC_C1_RX_IRQn);
|
||||
HAL_NVIC_DisableIRQ(IPCC_C1_TX_IRQn);
|
||||
/* USER CODE BEGIN IPCC_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END IPCC_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -1,263 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file : main.c
|
||||
* @brief : Main program body
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "dma.h"
|
||||
#include "ipcc.h"
|
||||
#include "rtc.h"
|
||||
#include "tim.h"
|
||||
#include "usart.h"
|
||||
#include "gpio.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
#include <stdbool.h>
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void SystemClock_Config(void);
|
||||
void PeriphCommonClock_Config(void);
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
volatile bool uart_rx_busy = false;
|
||||
volatile bool uart_tx_busy = false;
|
||||
uint8_t uart_rx_data[1];
|
||||
volatile bool queue_send = false;
|
||||
|
||||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
|
||||
//if (uart_rx_data[0] == 'T') {
|
||||
HAL_GPIO_TogglePin(GPIOB, LED4_Pin | LED5_Pin);
|
||||
//}
|
||||
uart_rx_busy = false;
|
||||
}
|
||||
|
||||
void HAL_UART_TXCpltCallback(UART_HandleTypeDef *huart) {
|
||||
HAL_GPIO_TogglePin(GPIOB, LED5_Pin);
|
||||
uart_tx_busy = false;
|
||||
}
|
||||
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
|
||||
if (htim->Instance == TIM2) {
|
||||
HAL_GPIO_TogglePin(GPIOB, LED4_Pin);
|
||||
queue_send = true;
|
||||
}
|
||||
}
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/**
|
||||
* @brief The application entry point.
|
||||
* @retval int
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* MCU Configuration--------------------------------------------------------*/
|
||||
|
||||
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
||||
HAL_Init();
|
||||
|
||||
/* USER CODE BEGIN Init */
|
||||
|
||||
/* USER CODE END Init */
|
||||
|
||||
/* Configure the system clock */
|
||||
SystemClock_Config();
|
||||
|
||||
/* Configure the peripherals common clocks */
|
||||
PeriphCommonClock_Config();
|
||||
|
||||
/* IPCC initialisation */
|
||||
MX_IPCC_Init();
|
||||
|
||||
/* USER CODE BEGIN SysInit */
|
||||
|
||||
/* USER CODE END SysInit */
|
||||
|
||||
/* Initialize all configured peripherals */
|
||||
MX_GPIO_Init();
|
||||
MX_DMA_Init();
|
||||
MX_RTC_Init();
|
||||
MX_USART1_UART_Init();
|
||||
MX_TIM2_Init();
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
|
||||
/* Infinite loop */
|
||||
/* USER CODE BEGIN WHILE */
|
||||
HAL_TIM_Base_Start_IT(&htim2);
|
||||
uint8_t uart_tx_data[1] = {'T'};
|
||||
while (1)
|
||||
{
|
||||
if (!uart_rx_busy) {
|
||||
HAL_UART_Receive_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
|
||||
uart_rx_busy = true;
|
||||
}
|
||||
|
||||
if (queue_send && (!uart_tx_busy)) {
|
||||
uart_tx_busy = true;
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
}
|
||||
/* USER CODE END WHILE */
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
}
|
||||
/* USER CODE END 3 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
/** Configure LSE Drive Capability
|
||||
*/
|
||||
HAL_PWR_EnableBkUpAccess();
|
||||
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
|
||||
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure.
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
|
||||
|RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 8;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
|
||||
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
|
||||
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Peripherals Common Clock Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void PeriphCommonClock_Config(void)
|
||||
{
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
|
||||
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
|
||||
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN Smps */
|
||||
|
||||
/* USER CODE END Smps */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
|
||||
/* USER CODE END 4 */
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler_Debug */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
__disable_irq();
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler_Debug */
|
||||
}
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief Reports the name of the source file and the source line number
|
||||
* where the assert_param error has occurred.
|
||||
* @param file: pointer to the source file name
|
||||
* @param line: assert_param error line source number
|
||||
* @retval None
|
||||
*/
|
||||
void assert_failed(uint8_t *file, uint32_t line)
|
||||
{
|
||||
/* USER CODE BEGIN 6 */
|
||||
/* User can add his own implementation to report the file name and line number,
|
||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||
/* USER CODE END 6 */
|
||||
}
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
@@ -1,47 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rf.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the RF instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "rf.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/* RF init function */
|
||||
void MX_RF_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN RF_Init 0 */
|
||||
|
||||
/* USER CODE END RF_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN RF_Init 1 */
|
||||
|
||||
/* USER CODE END RF_Init 1 */
|
||||
/* USER CODE BEGIN RF_Init 2 */
|
||||
|
||||
/* USER CODE END RF_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -1,108 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rtc.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the RTC instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "rtc.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
RTC_HandleTypeDef hrtc;
|
||||
|
||||
/* RTC init function */
|
||||
void MX_RTC_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN RTC_Init 0 */
|
||||
|
||||
/* USER CODE END RTC_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN RTC_Init 1 */
|
||||
|
||||
/* USER CODE END RTC_Init 1 */
|
||||
|
||||
/** Initialize RTC Only
|
||||
*/
|
||||
hrtc.Instance = RTC;
|
||||
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
hrtc.Init.AsynchPrediv = 127;
|
||||
hrtc.Init.SynchPrediv = 255;
|
||||
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
|
||||
if (HAL_RTC_Init(&hrtc) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN RTC_Init 2 */
|
||||
|
||||
/* USER CODE END RTC_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
|
||||
{
|
||||
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(rtcHandle->Instance==RTC)
|
||||
{
|
||||
/* USER CODE BEGIN RTC_MspInit 0 */
|
||||
|
||||
/* USER CODE END RTC_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* RTC clock enable */
|
||||
__HAL_RCC_RTC_ENABLE();
|
||||
__HAL_RCC_RTCAPB_CLK_ENABLE();
|
||||
/* USER CODE BEGIN RTC_MspInit 1 */
|
||||
|
||||
/* USER CODE END RTC_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
|
||||
{
|
||||
|
||||
if(rtcHandle->Instance==RTC)
|
||||
{
|
||||
/* USER CODE BEGIN RTC_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END RTC_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_RTC_DISABLE();
|
||||
__HAL_RCC_RTCAPB_CLK_DISABLE();
|
||||
/* USER CODE BEGIN RTC_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END RTC_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -1,247 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file standby.c
|
||||
* @author MCD Application Team
|
||||
* @brief Specific code for standby low power mode
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "app_entry.h"
|
||||
#include "app_common.h"
|
||||
#include "app_debug.h"
|
||||
#include "standby.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
uint32_t STBY_BackupMSP;
|
||||
uint32_t STBY_BackupIpccC1MR;
|
||||
uint32_t STBY_BackupVTOR;
|
||||
|
||||
uint32_t STBY_BootStatus;
|
||||
uint16_t STBY_DebugGpioaPinList = UINT16_MAX;
|
||||
uint16_t STBY_DebugGpiobPinList = UINT16_MAX;
|
||||
uint16_t STBY_DebugGpiocPinList = UINT16_MAX;
|
||||
uint16_t STBY_DtbGpioaPinList = UINT16_MAX;
|
||||
uint16_t STBY_DtbGpiobPinList = UINT16_MAX;
|
||||
|
||||
extern RTC_HandleTypeDef hrtc;
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void STBY_TriggerIT(void);
|
||||
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* This part may be updated by the user
|
||||
******************************************************************************/
|
||||
|
||||
void STBY_AppHwSave(void)
|
||||
{
|
||||
/* In this function HW parameters lost in standby can de saved.
|
||||
All RAM memory is in retention */
|
||||
/* USER CODE BEGIN STBY_AppHwSave_1 */
|
||||
|
||||
/* USER CODE END STBY_AppHwSave_1 */
|
||||
return;
|
||||
}
|
||||
|
||||
void STBY_AppHwRestore(void)
|
||||
{
|
||||
/* USER CODE BEGIN STBY_AppHwRestore_1 */
|
||||
|
||||
/* USER CODE END STBY_AppHwRestore_1 */
|
||||
|
||||
HAL_Init();
|
||||
HAL_ResumeTick();
|
||||
|
||||
/* In this user section add MX init functions present in main.c, except MX_RTC_Init() */
|
||||
/* USER CODE BEGIN STBY_AppHwRestore_2 */
|
||||
|
||||
/* USER CODE END STBY_AppHwRestore_2 */
|
||||
|
||||
STBY_TriggerIT();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Do not update code from this limit.
|
||||
******************************************************************************/
|
||||
|
||||
void STBY_SysHwSave(void)
|
||||
{
|
||||
STBY_BackupIpccC1MR = READ_REG(IPCC->C1MR);
|
||||
STBY_BackupVTOR = SCB->VTOR;
|
||||
|
||||
/* USER CODE BEGIN STBY_SysHwSave_1 */
|
||||
|
||||
/* USER CODE END STBY_SysHwSave_1 */
|
||||
return;
|
||||
}
|
||||
|
||||
void STBY_SysHwRestore(void)
|
||||
{
|
||||
/* USER CODE BEGIN STBY_SysHwRestore_1 */
|
||||
|
||||
/* USER CODE END STBY_SysHwRestore_1 */
|
||||
APPD_Init();
|
||||
|
||||
Init_Smps();
|
||||
Init_Exti();
|
||||
HAL_Init();
|
||||
|
||||
WRITE_REG(SCB->VTOR, STBY_BackupVTOR);
|
||||
|
||||
HW_IPCC_Init();
|
||||
WRITE_REG(IPCC->C1MR, STBY_BackupIpccC1MR);
|
||||
|
||||
if( !LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) )
|
||||
{
|
||||
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
|
||||
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
|
||||
}
|
||||
LL_HSEM_ReleaseLock( HSEM, CFG_HW_PWR_STANDBY_SEMID, 0 );
|
||||
|
||||
HW_TS_Init(hw_ts_InitMode_Limited, &hrtc);
|
||||
|
||||
LL_PWR_EnableSRAM2Retention();
|
||||
|
||||
/* USER CODE BEGIN STBY_SysHwRestore_2 */
|
||||
|
||||
/* USER CODE END STBY_SysHwRestore_2 */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t STBY_BootManager(void)
|
||||
{
|
||||
#if ( CFG_LPM_STANDBY_SUPPORTED != 0 )
|
||||
__HAL_RCC_HSEM_CLK_ENABLE();
|
||||
while( LL_HSEM_1StepLock( HSEM, CFG_HW_PWR_STANDBY_SEMID ) );
|
||||
|
||||
/* If a reset other than standby occurs, perform a full reset cycle */
|
||||
if( (LL_RCC_IsActiveFlag_IWDGRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_WWDGRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_BORRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_LPWRRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_OBLRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_PINRST() != FALSE) ||
|
||||
(LL_RCC_IsActiveFlag_SFTRST() != FALSE) )
|
||||
{
|
||||
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
|
||||
}
|
||||
|
||||
if( __HAL_PWR_GET_FLAG(PWR_FLAG_SB) != RESET )
|
||||
{
|
||||
__disable_irq( );
|
||||
|
||||
STBY_BootStatus = 1;
|
||||
}else{
|
||||
STBY_BootStatus = 0;
|
||||
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_C2SB);
|
||||
LL_HSEM_ReleaseLock( HSEM, CFG_HW_PWR_STANDBY_SEMID, 0 );
|
||||
}
|
||||
#else
|
||||
STBY_BootStatus = 0;
|
||||
#endif
|
||||
|
||||
return STBY_BootStatus;
|
||||
}
|
||||
|
||||
static void STBY_TriggerIT(void)
|
||||
{
|
||||
/* If system has been woken-up by an RTC alarm,
|
||||
* a software event must be generated to trigger the IT.
|
||||
* NVIC and EXTI must be reconfigured properly before triggering the event.
|
||||
*/
|
||||
if((__HAL_RTC_ALARM_GET_FLAG((RTC_HandleTypeDef *)&hrtc, RTC_FLAG_ALRAF) != 0) ||
|
||||
(__HAL_RTC_ALARM_GET_FLAG((RTC_HandleTypeDef *)&hrtc, RTC_FLAG_ALRBF) != 0) )
|
||||
{
|
||||
__HAL_RTC_ALARM_EXTI_GENERATE_SWIT();
|
||||
}
|
||||
|
||||
/* If system has been woken-up by a wake up pin,
|
||||
* a software event must be generated to trigger the IT.
|
||||
* NVIC and EXTI must be reconfigured properly before triggering the event.
|
||||
*/
|
||||
if(HAL_PWREx_GetWakeupFlag(PWR_FLAG_WUF1) != 0)
|
||||
{
|
||||
if( (LL_SYSCFG_GetEXTISource(LL_SYSCFG_EXTI_LINE0) == LL_SYSCFG_EXTI_PORTA) )
|
||||
{
|
||||
if(((READ_BIT(PWR->CR4, PWR_CR4_WP1) >> PWR_CR4_WP1_Pos) == 0) &&
|
||||
(LL_EXTI_IsEnabledRisingTrig_0_31(LL_EXTI_LINE_0) == 1) )
|
||||
{
|
||||
LL_EXTI_GenerateSWI_0_31(LL_EXTI_LINE_0);
|
||||
}
|
||||
if(((READ_BIT(PWR->CR4, PWR_CR4_WP1) >> PWR_CR4_WP1_Pos) == 1) &&
|
||||
(LL_EXTI_IsEnabledFallingTrig_0_31(LL_EXTI_LINE_0) == 1) )
|
||||
{
|
||||
LL_EXTI_GenerateSWI_0_31(LL_EXTI_LINE_0);
|
||||
}
|
||||
}
|
||||
HAL_PWREx_ClearWakeupFlag(PWR_FLAG_WUF1);
|
||||
}
|
||||
|
||||
if(HAL_PWREx_GetWakeupFlag(PWR_FLAG_WUF4) != 0)
|
||||
{
|
||||
if( (LL_SYSCFG_GetEXTISource(LL_SYSCFG_EXTI_LINE2) == LL_SYSCFG_EXTI_PORTA) )
|
||||
{
|
||||
if(((READ_BIT(PWR->CR4, PWR_CR4_WP4) >> PWR_CR4_WP4_Pos) == 0) &&
|
||||
(LL_EXTI_IsEnabledRisingTrig_0_31(LL_EXTI_LINE_2) == 1) )
|
||||
{
|
||||
LL_EXTI_GenerateSWI_0_31(LL_EXTI_LINE_2);
|
||||
}
|
||||
if(((READ_BIT(PWR->CR4, PWR_CR4_WP4) >> PWR_CR4_WP4_Pos) == 1) &&
|
||||
(LL_EXTI_IsEnabledFallingTrig_0_31(LL_EXTI_LINE_2) == 1) )
|
||||
{
|
||||
LL_EXTI_GenerateSWI_0_31(LL_EXTI_LINE_2);
|
||||
}
|
||||
}
|
||||
HAL_PWREx_ClearWakeupFlag(PWR_FLAG_WUF4);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -1,425 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
***************************************************************************************
|
||||
* @file stm32_lpm_if.c
|
||||
* @author MCD Application Team
|
||||
* @brief Low layer function to enter/exit low power modes (stop, sleep).
|
||||
***************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32_lpm_if.h"
|
||||
#include "stm32_lpm.h"
|
||||
#include "app_conf.h"
|
||||
#include "main.h"
|
||||
#include "standby.h"
|
||||
/* USER CODE BEGIN include */
|
||||
|
||||
/* USER CODE END include */
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
const struct UTIL_LPM_Driver_s UTIL_PowerDriver =
|
||||
{
|
||||
PWR_EnterSleepMode,
|
||||
PWR_ExitSleepMode,
|
||||
|
||||
PWR_EnterStopMode,
|
||||
PWR_ExitStopMode,
|
||||
|
||||
PWR_EnterOffMode,
|
||||
PWR_ExitOffMode,
|
||||
};
|
||||
|
||||
extern RTC_HandleTypeDef hrtc;
|
||||
|
||||
void CPUcontextSave(void); /* this function is implemented in startup assembly file */
|
||||
void SystemClock_Config(void);
|
||||
void PeriphCommonClock_Config(void);
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void Switch_On_HSI(void);
|
||||
static void EnterLowPower(void);
|
||||
static void ExitLowPower(void);
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
static void ExitLowPower_standby(void);
|
||||
#endif
|
||||
/* USER CODE BEGIN Private_Function_Prototypes */
|
||||
|
||||
/* USER CODE END Private_Function_Prototypes */
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Private_Typedef */
|
||||
|
||||
/* USER CODE END Private_Typedef */
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Private_Define */
|
||||
|
||||
/* USER CODE END Private_Define */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Private_Macro */
|
||||
|
||||
/* USER CODE END Private_Macro */
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Private_Variables */
|
||||
|
||||
/* USER CODE END Private_Variables */
|
||||
|
||||
/* Functions Definition ------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enters Low Power Off Mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_EnterOffMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_EnterOffMode_1 */
|
||||
|
||||
/* USER CODE END PWR_EnterOffMode_1 */
|
||||
/**
|
||||
* The systick should be disabled for the same reason than when the device enters stop mode because
|
||||
* at this time, the device may enter either OffMode or StopMode.
|
||||
*/
|
||||
HAL_SuspendTick();
|
||||
__HAL_RCC_CLEAR_RESET_FLAGS();
|
||||
|
||||
EnterLowPower();
|
||||
|
||||
/************************************************************************************
|
||||
* ENTER OFF MODE
|
||||
***********************************************************************************/
|
||||
/*
|
||||
* There is no risk to clear all the WUF here because in the current implementation, this API is called
|
||||
* in critical section. If an interrupt occurs while in that critical section before that point,
|
||||
* the flag is set and will be cleared here but the system will not enter Off Mode
|
||||
* because an interrupt is pending in the NVIC. The ISR will be executed when moving out
|
||||
* of this critical section
|
||||
*/
|
||||
LL_PWR_ClearFlag_WU();
|
||||
|
||||
LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
|
||||
|
||||
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
|
||||
/**
|
||||
* This option is used to ensure that store operations are completed
|
||||
*/
|
||||
#if defined (__CC_ARM) || defined (__ARMCC_VERSION)
|
||||
__force_stores();
|
||||
#endif
|
||||
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
LL_EXTI_EnableRisingTrig_32_63(LL_EXTI_LINE_40);
|
||||
LL_EXTI_EnableEvent_32_63(LL_EXTI_LINE_40);
|
||||
|
||||
STBY_AppHwSave();
|
||||
STBY_SysHwSave();
|
||||
|
||||
CPUcontextSave();/* this function will call WFI instruction */
|
||||
#endif
|
||||
|
||||
/* USER CODE BEGIN PWR_EnterOffMode_2 */
|
||||
|
||||
/* USER CODE END PWR_EnterOffMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits Low Power Off Mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_ExitOffMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_ExitOffMode_1 */
|
||||
|
||||
/* USER CODE END PWR_ExitOffMode_1 */
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
if(STBY_BootStatus != 0)
|
||||
{
|
||||
STBY_SysHwRestore();
|
||||
ExitLowPower_standby();
|
||||
STBY_AppHwRestore();
|
||||
}
|
||||
else
|
||||
{
|
||||
ExitLowPower();
|
||||
}
|
||||
#endif
|
||||
/* USER CODE BEGIN PWR_ExitOffMode_2 */
|
||||
|
||||
/* USER CODE END PWR_ExitOffMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Low Power Stop Mode
|
||||
* @note ARM exists the function when waking up
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_EnterStopMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_EnterStopMode_1 */
|
||||
|
||||
/* USER CODE END PWR_EnterStopMode_1 */
|
||||
/**
|
||||
* When HAL_DBGMCU_EnableDBGStopMode() is called to keep the debugger active in Stop Mode,
|
||||
* the systick shall be disabled otherwise the cpu may crash when moving out from stop mode
|
||||
*
|
||||
* When in production, the HAL_DBGMCU_EnableDBGStopMode() is not called so that the device can reach best power consumption
|
||||
* However, the systick should be disabled anyway to avoid the case when it is about to expire at the same time the device enters
|
||||
* stop mode (this will abort the Stop Mode entry).
|
||||
*/
|
||||
HAL_SuspendTick();
|
||||
|
||||
/**
|
||||
* This function is called from CRITICAL SECTION
|
||||
*/
|
||||
EnterLowPower();
|
||||
|
||||
/************************************************************************************
|
||||
* ENTER STOP MODE
|
||||
***********************************************************************************/
|
||||
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
|
||||
|
||||
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
|
||||
/**
|
||||
* This option is used to ensure that store operations are completed
|
||||
*/
|
||||
#if defined (__CC_ARM) || defined (__ARMCC_VERSION)
|
||||
__force_stores();
|
||||
#endif
|
||||
|
||||
__WFI();
|
||||
|
||||
/* USER CODE BEGIN PWR_EnterStopMode_2 */
|
||||
|
||||
/* USER CODE END PWR_EnterStopMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits Low Power Stop Mode
|
||||
* @note Enable the pll at 32MHz
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_ExitStopMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_ExitStopMode_1 */
|
||||
|
||||
/* USER CODE END PWR_ExitStopMode_1 */
|
||||
/**
|
||||
* This function is called from CRITICAL SECTION
|
||||
*/
|
||||
ExitLowPower();
|
||||
|
||||
HAL_ResumeTick();
|
||||
/* USER CODE BEGIN PWR_ExitStopMode_2 */
|
||||
|
||||
/* USER CODE END PWR_ExitStopMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Low Power Sleep Mode
|
||||
* @note ARM exits the function when waking up
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_EnterSleepMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_EnterSleepMode_1 */
|
||||
|
||||
/* USER CODE END PWR_EnterSleepMode_1 */
|
||||
|
||||
HAL_SuspendTick();
|
||||
|
||||
/************************************************************************************
|
||||
* ENTER SLEEP MODE
|
||||
***********************************************************************************/
|
||||
LL_LPM_EnableSleep(); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
|
||||
/**
|
||||
* This option is used to ensure that store operations are completed
|
||||
*/
|
||||
#if defined (__CC_ARM) || defined (__ARMCC_VERSION)
|
||||
__force_stores();
|
||||
#endif
|
||||
|
||||
__WFI();
|
||||
/* USER CODE BEGIN PWR_EnterSleepMode_2 */
|
||||
|
||||
/* USER CODE END PWR_EnterSleepMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits Low Power Sleep Mode
|
||||
* @note ARM exits the function when waking up
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PWR_ExitSleepMode(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_ExitSleepMode_1 */
|
||||
|
||||
/* USER CODE END PWR_ExitSleepMode_1 */
|
||||
HAL_ResumeTick();
|
||||
/* USER CODE BEGIN PWR_ExitSleepMode_2 */
|
||||
|
||||
/* USER CODE END PWR_ExitSleepMode_2 */
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Weak CPUcontextSave function definition to implement in startup file.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
__WEAK void CPUcontextSave(void)
|
||||
{
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
/*
|
||||
* If you are here, you have to update your startup_stm32wb15xx_cm4.s file to
|
||||
* implement CPUcontextSave function like done in latest STM32CubeWB package
|
||||
* into STM32WB15 BLE applications.
|
||||
*/
|
||||
Error_Handler();
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
*
|
||||
* LOCAL FUNCTIONS
|
||||
*
|
||||
*************************************************************/
|
||||
/**
|
||||
* @brief Setup the system to enter either stop or off mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void EnterLowPower(void)
|
||||
{
|
||||
/**
|
||||
* This function is called from CRITICAL SECTION
|
||||
*/
|
||||
|
||||
while(LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
|
||||
|
||||
if (! LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID))
|
||||
{
|
||||
if(LL_PWR_IsActiveFlag_C2DS() || LL_PWR_IsActiveFlag_C2SB())
|
||||
{
|
||||
/* Release ENTRY_STOP_MODE semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
|
||||
|
||||
Switch_On_HSI();
|
||||
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Switch_On_HSI();
|
||||
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_0);
|
||||
}
|
||||
|
||||
/* Release RCC semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restore the system to exit stop mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void ExitLowPower(void)
|
||||
{
|
||||
/* Release ENTRY_STOP_MODE semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
|
||||
|
||||
while(LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
|
||||
|
||||
if(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
|
||||
{
|
||||
/* Restore the clock configuration of the application in this user section */
|
||||
/* USER CODE BEGIN ExitLowPower_1 */
|
||||
|
||||
/* USER CODE END ExitLowPower_1 */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If the application is not running on HSE restore the clock configuration in this user section */
|
||||
/* USER CODE BEGIN ExitLowPower_2 */
|
||||
|
||||
/* USER CODE END ExitLowPower_2 */
|
||||
}
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
|
||||
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
|
||||
#endif
|
||||
|
||||
/* Release RCC semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#if (CFG_LPM_STANDBY_SUPPORTED != 0)
|
||||
/**
|
||||
* @brief Restore the system to exit standby mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void ExitLowPower_standby(void)
|
||||
{
|
||||
/* Release ENTRY_STOP_MODE semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
|
||||
|
||||
while(LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
|
||||
/* USER CODE BEGIN ExitLowPower_standby */
|
||||
|
||||
/* USER CODE END ExitLowPower_standby */
|
||||
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
|
||||
|
||||
/* Release RCC semaphore */
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Switch the system clock on HSI
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void Switch_On_HSI(void)
|
||||
{
|
||||
LL_RCC_HSI_Enable();
|
||||
while(!LL_RCC_HSI_IsReady());
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
|
||||
LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
|
||||
return;
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN Private_Functions */
|
||||
|
||||
/* USER CODE END Private_Functions */
|
||||
|
||||
@@ -1,91 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_msp.c
|
||||
* @brief This file provides code for the MSP Initialization
|
||||
* and de-Initialization codes.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Define */
|
||||
|
||||
/* USER CODE END Define */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Macro */
|
||||
|
||||
/* USER CODE END Macro */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* External functions --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ExternalFunctions */
|
||||
|
||||
/* USER CODE END ExternalFunctions */
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
/**
|
||||
* Initializes the Global MSP.
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN MspInit 0 */
|
||||
|
||||
/* USER CODE END MspInit 0 */
|
||||
|
||||
__HAL_RCC_HSEM_CLK_ENABLE();
|
||||
|
||||
/* System interrupt init*/
|
||||
|
||||
/* Peripheral interrupt init */
|
||||
/* RCC_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(RCC_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(RCC_IRQn);
|
||||
/* PWR_SOTF_BLEACT_RFPHASE_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(PWR_SOTF_BLEACT_RFPHASE_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(PWR_SOTF_BLEACT_RFPHASE_IRQn);
|
||||
/* HSEM_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(HSEM_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(HSEM_IRQn);
|
||||
|
||||
/* USER CODE BEGIN MspInit 1 */
|
||||
|
||||
/* USER CODE END MspInit 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
@@ -1,331 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_it.c
|
||||
* @brief Interrupt Service Routines.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "stm32wbxx_it.h"
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
extern IPCC_HandleTypeDef hipcc;
|
||||
extern TIM_HandleTypeDef htim2;
|
||||
extern DMA_HandleTypeDef hdma_usart1_rx;
|
||||
extern DMA_HandleTypeDef hdma_usart1_tx;
|
||||
extern UART_HandleTypeDef huart1;
|
||||
/* USER CODE BEGIN EV */
|
||||
|
||||
/* USER CODE END EV */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex Processor Interruption and Exception Handlers */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief This function handles Non maskable interrupt.
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
||||
|
||||
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END NonMaskableInt_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard fault interrupt.
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN HardFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END HardFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
|
||||
/* USER CODE END W1_HardFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory management fault.
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
||||
|
||||
/* USER CODE END MemoryManagement_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
|
||||
/* USER CODE END W1_MemoryManagement_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Prefetch fault, memory access fault.
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN BusFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END BusFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
|
||||
/* USER CODE END W1_BusFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Undefined instruction or illegal state.
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END UsageFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
|
||||
/* USER CODE END W1_UsageFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles System service call via SWI instruction.
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN SVCall_IRQn 0 */
|
||||
|
||||
/* USER CODE END SVCall_IRQn 0 */
|
||||
/* USER CODE BEGIN SVCall_IRQn 1 */
|
||||
|
||||
/* USER CODE END SVCall_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug monitor.
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
|
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 0 */
|
||||
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Pendable request for system service.
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN PendSV_IRQn 0 */
|
||||
|
||||
/* USER CODE END PendSV_IRQn 0 */
|
||||
/* USER CODE BEGIN PendSV_IRQn 1 */
|
||||
|
||||
/* USER CODE END PendSV_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles System tick timer.
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN SysTick_IRQn 0 */
|
||||
|
||||
/* USER CODE END SysTick_IRQn 0 */
|
||||
HAL_IncTick();
|
||||
/* USER CODE BEGIN SysTick_IRQn 1 */
|
||||
|
||||
/* USER CODE END SysTick_IRQn 1 */
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32WBxx Peripheral Interrupt Handlers */
|
||||
/* Add here the Interrupt Handlers for the used peripherals. */
|
||||
/* For the available peripheral interrupt handler names, */
|
||||
/* please refer to the startup file (startup_stm32wbxx.s). */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles RCC global interrupt.
|
||||
*/
|
||||
void RCC_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN RCC_IRQn 0 */
|
||||
|
||||
/* USER CODE END RCC_IRQn 0 */
|
||||
/* USER CODE BEGIN RCC_IRQn 1 */
|
||||
|
||||
/* USER CODE END RCC_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 channel1 global interrupt.
|
||||
*/
|
||||
void DMA1_Channel1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Channel1_IRQn 0 */
|
||||
HAL_DMA_IRQHandler(&hdma_usart1_rx);
|
||||
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Channel1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 channel2 global interrupt.
|
||||
*/
|
||||
void DMA1_Channel2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Channel2_IRQn 0 */
|
||||
HAL_DMA_IRQHandler(&hdma_usart1_tx);
|
||||
/* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Channel2_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles TIM2 global interrupt.
|
||||
*/
|
||||
void TIM2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_IRQn 0 */
|
||||
|
||||
/* USER CODE END TIM2_IRQn 0 */
|
||||
HAL_TIM_IRQHandler(&htim2);
|
||||
/* USER CODE BEGIN TIM2_IRQn 1 */
|
||||
|
||||
/* USER CODE END TIM2_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USART1 global interrupt.
|
||||
*/
|
||||
void USART1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_IRQn 0 */
|
||||
|
||||
/* USER CODE END USART1_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart1);
|
||||
/* USER CODE BEGIN USART1_IRQn 1 */
|
||||
|
||||
/* USER CODE END USART1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PWR switching on the fly interrupt, PWR end of BLE activity interrupt, PWR end of critical radio phase interrupt.
|
||||
*/
|
||||
void PWR_SOTF_BLEACT_RFPHASE_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN PWR_SOTF_BLEACT_RFPHASE_IRQn 0 */
|
||||
|
||||
/* USER CODE END PWR_SOTF_BLEACT_RFPHASE_IRQn 0 */
|
||||
/* USER CODE BEGIN PWR_SOTF_BLEACT_RFPHASE_IRQn 1 */
|
||||
|
||||
/* USER CODE END PWR_SOTF_BLEACT_RFPHASE_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles IPCC RX occupied interrupt.
|
||||
*/
|
||||
void IPCC_C1_RX_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */
|
||||
|
||||
/* USER CODE END IPCC_C1_RX_IRQn 0 */
|
||||
HAL_IPCC_RX_IRQHandler(&hipcc);
|
||||
/* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */
|
||||
|
||||
/* USER CODE END IPCC_C1_RX_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles IPCC TX free interrupt.
|
||||
*/
|
||||
void IPCC_C1_TX_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */
|
||||
|
||||
/* USER CODE END IPCC_C1_TX_IRQn 0 */
|
||||
HAL_IPCC_TX_IRQHandler(&hipcc);
|
||||
/* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */
|
||||
|
||||
/* USER CODE END IPCC_C1_TX_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles HSEM global interrupt.
|
||||
*/
|
||||
void HSEM_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN HSEM_IRQn 0 */
|
||||
|
||||
/* USER CODE END HSEM_IRQn 0 */
|
||||
HAL_HSEM_IRQHandler();
|
||||
/* USER CODE BEGIN HSEM_IRQn 1 */
|
||||
|
||||
/* USER CODE END HSEM_IRQn 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
@@ -1,244 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file syscalls.c
|
||||
* @author Auto-generated by STM32CubeMX
|
||||
* @brief Minimal System calls file
|
||||
*
|
||||
* For more information about which c-functions
|
||||
* need which of these lowlevel functions
|
||||
* please consult the Newlib or Picolibc libc-manual
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2025 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
#include <sys/stat.h>
|
||||
#include <stdlib.h>
|
||||
#include <errno.h>
|
||||
#include <stdio.h>
|
||||
#include <signal.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/times.h>
|
||||
|
||||
|
||||
/* Variables */
|
||||
extern int __io_putchar(int ch) __attribute__((weak));
|
||||
extern int __io_getchar(void) __attribute__((weak));
|
||||
|
||||
|
||||
char *__env[1] = { 0 };
|
||||
char **environ = __env;
|
||||
|
||||
|
||||
/* Functions */
|
||||
void initialise_monitor_handles()
|
||||
{
|
||||
}
|
||||
|
||||
int _getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _kill(int pid, int sig)
|
||||
{
|
||||
(void)pid;
|
||||
(void)sig;
|
||||
errno = EINVAL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit (int status)
|
||||
{
|
||||
_kill(status, -1);
|
||||
while (1) {} /* Make sure we hang here */
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
||||
{
|
||||
(void)file;
|
||||
int DataIdx;
|
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||
{
|
||||
*ptr++ = __io_getchar();
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
||||
{
|
||||
(void)file;
|
||||
int DataIdx;
|
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||
{
|
||||
__io_putchar(*ptr++);
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
int _close(int file)
|
||||
{
|
||||
(void)file;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
int _fstat(int file, struct stat *st)
|
||||
{
|
||||
(void)file;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _isatty(int file)
|
||||
{
|
||||
(void)file;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int file, int ptr, int dir)
|
||||
{
|
||||
(void)file;
|
||||
(void)ptr;
|
||||
(void)dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _open(char *path, int flags, ...)
|
||||
{
|
||||
(void)path;
|
||||
(void)flags;
|
||||
/* Pretend like we always fail */
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _wait(int *status)
|
||||
{
|
||||
(void)status;
|
||||
errno = ECHILD;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(char *name)
|
||||
{
|
||||
(void)name;
|
||||
errno = ENOENT;
|
||||
return -1;
|
||||
}
|
||||
|
||||
clock_t _times(struct tms *buf)
|
||||
{
|
||||
(void)buf;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *file, struct stat *st)
|
||||
{
|
||||
(void)file;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _link(char *old, char *new)
|
||||
{
|
||||
(void)old;
|
||||
(void)new;
|
||||
errno = EMLINK;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fork(void)
|
||||
{
|
||||
errno = EAGAIN;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _execve(char *name, char **argv, char **env)
|
||||
{
|
||||
(void)name;
|
||||
(void)argv;
|
||||
(void)env;
|
||||
errno = ENOMEM;
|
||||
return -1;
|
||||
}
|
||||
|
||||
// --- Picolibc Specific Section ---
|
||||
#if defined(__PICOLIBC__)
|
||||
|
||||
/**
|
||||
* @brief Picolibc helper function to output a character to a FILE stream.
|
||||
* This redirects the output to the low-level __io_putchar function.
|
||||
* @param c Character to write.
|
||||
* @param file FILE stream pointer (ignored).
|
||||
* @retval int The character written.
|
||||
*/
|
||||
static int starm_putc(char c, FILE *file)
|
||||
{
|
||||
(void) file;
|
||||
__io_putchar(c);
|
||||
return c;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Picolibc helper function to input a character from a FILE stream.
|
||||
* This redirects the input from the low-level __io_getchar function.
|
||||
* @param file FILE stream pointer (ignored).
|
||||
* @retval int The character read, cast to an unsigned char then int.
|
||||
*/
|
||||
static int starm_getc(FILE *file)
|
||||
{
|
||||
unsigned char c;
|
||||
(void) file;
|
||||
c = __io_getchar();
|
||||
return c;
|
||||
}
|
||||
|
||||
// Define and initialize the standard I/O streams for Picolibc.
|
||||
// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure.
|
||||
// _FDEV_SETUP_RW indicates the stream is for reading and writing.
|
||||
static FILE __stdio = FDEV_SETUP_STREAM(starm_putc,
|
||||
starm_getc,
|
||||
NULL,
|
||||
_FDEV_SETUP_RW);
|
||||
|
||||
// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream.
|
||||
// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.).
|
||||
FILE *const stdin = &__stdio;
|
||||
__strong_reference(stdin, stdout);
|
||||
__strong_reference(stdin, stderr);
|
||||
|
||||
// Create strong aliases mapping standard C library function names (without underscore)
|
||||
// to the implemented system call stubs (with underscore). Picolibc uses these
|
||||
// standard names internally, so this linking is required.
|
||||
__strong_reference(_read, read);
|
||||
__strong_reference(_write, write);
|
||||
__strong_reference(_times, times);
|
||||
__strong_reference(_execve, execve);
|
||||
__strong_reference(_fork, fork);
|
||||
__strong_reference(_link, link);
|
||||
__strong_reference(_unlink, unlink);
|
||||
__strong_reference(_stat, stat);
|
||||
__strong_reference(_wait, wait);
|
||||
__strong_reference(_open, open);
|
||||
__strong_reference(_close, close);
|
||||
__strong_reference(_lseek, lseek);
|
||||
__strong_reference(_isatty, isatty);
|
||||
__strong_reference(_fstat, fstat);
|
||||
__strong_reference(_exit, exit);
|
||||
__strong_reference(_kill, kill);
|
||||
__strong_reference(_getpid, getpid);
|
||||
|
||||
#endif //__PICOLIBC__
|
||||
@@ -1,87 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file sysmem.c
|
||||
* @author Generated by STM32CubeMX
|
||||
* @brief System Memory calls file
|
||||
*
|
||||
* For more information about which C functions
|
||||
* need which of these lowlevel functions
|
||||
* please consult the Newlib or Picolibc libc manual
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2025 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/**
|
||||
* Pointer to the current high watermark of the heap usage
|
||||
*/
|
||||
static uint8_t *__sbrk_heap_end = NULL;
|
||||
|
||||
/**
|
||||
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
|
||||
* and others from the C library
|
||||
*
|
||||
* @verbatim
|
||||
* ############################################################################
|
||||
* # .data # .bss # newlib heap # MSP stack #
|
||||
* # # # # Reserved by _Min_Stack_Size #
|
||||
* ############################################################################
|
||||
* ^-- RAM start ^-- _end _estack, RAM end --^
|
||||
* @endverbatim
|
||||
*
|
||||
* This implementation starts allocating at the '_end' linker symbol
|
||||
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
|
||||
* The implementation considers '_estack' linker symbol to be RAM end
|
||||
* NOTE: If the MSP stack, at any point during execution, grows larger than the
|
||||
* reserved size, please increase the '_Min_Stack_Size'.
|
||||
*
|
||||
* @param incr Memory size
|
||||
* @return Pointer to allocated memory
|
||||
*/
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern uint8_t _end; /* Symbol defined in the linker script */
|
||||
extern uint8_t _estack; /* Symbol defined in the linker script */
|
||||
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
||||
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
||||
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
||||
uint8_t *prev_heap_end;
|
||||
|
||||
/* Initialize heap end at first call */
|
||||
if (NULL == __sbrk_heap_end)
|
||||
{
|
||||
__sbrk_heap_end = &_end;
|
||||
}
|
||||
|
||||
/* Protect heap from growing into the reserved MSP stack */
|
||||
if (__sbrk_heap_end + incr > max_heap)
|
||||
{
|
||||
errno = ENOMEM;
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
prev_heap_end = __sbrk_heap_end;
|
||||
__sbrk_heap_end += incr;
|
||||
|
||||
return (void *)prev_heap_end;
|
||||
}
|
||||
|
||||
#if defined(__PICOLIBC__)
|
||||
// Picolibc expects syscalls without the leading underscore.
|
||||
// This creates a strong alias so that
|
||||
// calls to `sbrk()` are resolved to our `_sbrk()` implementation.
|
||||
__strong_reference(_sbrk, sbrk);
|
||||
#endif
|
||||
@@ -1,378 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32wbxx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32wbxx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
|
||||
#endif /* LSI_VALUE */
|
||||
|
||||
#if !defined (LSE_VALUE)
|
||||
#if defined(STM32WB5Mxx)
|
||||
#define LSE_VALUE 32774U /*!< Value of the LSE oscillator in Hz */
|
||||
#else
|
||||
#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
|
||||
#endif /* STM32WB5Mxx */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
|
||||
CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
|
||||
at address 0x00 which correspond to automatic remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
||||
will be done in Flash. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#if !defined(VECT_TAB_OFFSET)
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_OFFSET */
|
||||
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#if !defined(VECT_TAB_OFFSET)
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_OFFSET */
|
||||
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
|
||||
|
||||
const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
|
||||
|
||||
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
|
||||
|
||||
const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
|
||||
4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL
|
||||
}; /* 0UL values are incorrect cases */
|
||||
|
||||
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB1Mxx)
|
||||
const uint32_t SmpsPrescalerTable[4UL][6UL] = {{1UL, 3UL, 2UL, 2UL, 1UL, 2UL}, \
|
||||
{2UL, 6UL, 4UL, 3UL, 2UL, 4UL}, \
|
||||
{4UL, 12UL, 8UL, 6UL, 4UL, 8UL}, \
|
||||
{4UL, 12UL, 8UL, 6UL, 4UL, 8UL}
|
||||
};
|
||||
#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx || STM32WB15xx || STM32WB1Mxx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
|
||||
#endif /* FPU */
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00070000U;
|
||||
|
||||
/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFAF6FEFBU;
|
||||
|
||||
/*!< Reset LSI1 and LSI2 bits */
|
||||
RCC->CSR &= (uint32_t)0xFFFFFFFAU;
|
||||
|
||||
/*!< Reset HSI48ON bit */
|
||||
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x22041000U;
|
||||
|
||||
#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
|
||||
/* Reset PLLSAI1CFGR register */
|
||||
RCC->PLLSAI1CFGR = 0x22041000U;
|
||||
#endif /* STM32WB55xx || STM32WB5Mxx */
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp, msirange, pllvco, pllr, pllsource, pllm;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
|
||||
/*MSI frequency range in Hz*/
|
||||
msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
/* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
|
||||
|
||||
if (pllsource == 0x02UL) /* HSI used as PLL clock source */
|
||||
{
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
}
|
||||
else if (pllsource == 0x03UL) /* HSE used as PLL clock source */
|
||||
{
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
}
|
||||
else /* MSI used as PLL clock source */
|
||||
{
|
||||
pllvco = (msirange / pllm);
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
|
||||
|
||||
SystemCoreClock = pllvco / pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK1 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||||
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = SystemCoreClock / tmp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1,112 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tim.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the TIM instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tim.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
TIM_HandleTypeDef htim2;
|
||||
|
||||
/* TIM2 init function */
|
||||
void MX_TIM2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM2_Init 0 */
|
||||
|
||||
/* USER CODE END TIM2_Init 0 */
|
||||
|
||||
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM2_Init 1 */
|
||||
|
||||
/* USER CODE END TIM2_Init 1 */
|
||||
htim2.Instance = TIM2;
|
||||
htim2.Init.Prescaler = 63999;
|
||||
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim2.Init.Period = 99;
|
||||
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
|
||||
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||||
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM2_Init 2 */
|
||||
|
||||
/* USER CODE END TIM2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
||||
{
|
||||
|
||||
if(tim_baseHandle->Instance==TIM2)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM2_MspInit 0 */
|
||||
/* TIM2 clock enable */
|
||||
__HAL_RCC_TIM2_CLK_ENABLE();
|
||||
|
||||
/* TIM2 interrupt Init */
|
||||
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(TIM2_IRQn);
|
||||
/* USER CODE BEGIN TIM2_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM2_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
|
||||
{
|
||||
|
||||
if(tim_baseHandle->Instance==TIM2)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM2_CLK_DISABLE();
|
||||
|
||||
/* TIM2 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(TIM2_IRQn);
|
||||
/* USER CODE BEGIN TIM2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM2_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -1,197 +0,0 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file usart.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the USART instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usart.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
UART_HandleTypeDef huart1;
|
||||
DMA_HandleTypeDef hdma_usart1_rx;
|
||||
DMA_HandleTypeDef hdma_usart1_tx;
|
||||
|
||||
/* USART1 init function */
|
||||
|
||||
void MX_USART1_UART_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN USART1_Init 0 */
|
||||
|
||||
/* USER CODE END USART1_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN USART1_Init 1 */
|
||||
|
||||
/* USER CODE END USART1_Init 1 */
|
||||
huart1.Instance = USART1;
|
||||
huart1.Init.BaudRate = 115200;
|
||||
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
huart1.Init.StopBits = UART_STOPBITS_1;
|
||||
huart1.Init.Parity = UART_PARITY_NONE;
|
||||
huart1.Init.Mode = UART_MODE_TX_RX;
|
||||
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
if (HAL_UART_Init(&huart1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN USART1_Init 2 */
|
||||
|
||||
/* USER CODE END USART1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(uartHandle->Instance==USART1)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_MspInit 0 */
|
||||
|
||||
/* USER CODE END USART1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||||
PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* USART1 clock enable */
|
||||
__HAL_RCC_USART1_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**USART1 GPIO Configuration
|
||||
PB6 ------> USART1_TX
|
||||
PA10 ------> USART1_RX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_10;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USART1 DMA Init */
|
||||
/* USART1_RX Init */
|
||||
hdma_usart1_rx.Instance = DMA1_Channel1;
|
||||
hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX;
|
||||
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);
|
||||
|
||||
/* USART1_TX Init */
|
||||
hdma_usart1_tx.Instance = DMA1_Channel2;
|
||||
hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
|
||||
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
|
||||
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
|
||||
|
||||
/* USART1 interrupt Init */
|
||||
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
||||
/* USER CODE BEGIN USART1_MspInit 1 */
|
||||
|
||||
/* USER CODE END USART1_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
|
||||
{
|
||||
|
||||
if(uartHandle->Instance==USART1)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END USART1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_USART1_CLK_DISABLE();
|
||||
|
||||
/**USART1 GPIO Configuration
|
||||
PB6 ------> USART1_TX
|
||||
PA10 ------> USART1_RX
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10);
|
||||
|
||||
/* USART1 DMA DeInit */
|
||||
HAL_DMA_DeInit(uartHandle->hdmarx);
|
||||
HAL_DMA_DeInit(uartHandle->hdmatx);
|
||||
|
||||
/* USART1 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(USART1_IRQn);
|
||||
/* USER CODE BEGIN USART1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END USART1_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -65,43 +65,54 @@ void PeriphCommonClock_Config(void);
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
uint8_t uart_rx_data[1028];
|
||||
__attribute__((aligned(4))) uint8_t uart_rx_data[1028];
|
||||
__attribute__((aligned(4))) uint8_t ble_out_data[1028];
|
||||
uint8_t uart_tx_data[1] = {'R'};
|
||||
bool ready_for_data = false;
|
||||
|
||||
volatile uint32_t xfer_len;
|
||||
volatile uint32_t xfer_len = sizeof(ble_out_data);
|
||||
volatile uint32_t last_send = 0;
|
||||
|
||||
volatile bool do_notify = false;
|
||||
void SendNotifyTask(void) {
|
||||
extern uint16_t SizeArrread;
|
||||
if (!do_notify) {
|
||||
return;
|
||||
}
|
||||
for (int i = 0; 128 * i < xfer_len; ++i) {
|
||||
for (int i = 0; i < xfer_len; i += 248) {
|
||||
if (xfer_len - i >= 248) {
|
||||
SizeArrread = 248;
|
||||
} else {
|
||||
SizeArrread = xfer_len - i;
|
||||
}
|
||||
Custom_STM_App_Update_Char(
|
||||
CUSTOM_STM_ARRREAD,
|
||||
uart_rx_data + i * 128
|
||||
ble_out_data + i
|
||||
);
|
||||
}
|
||||
last_send = TIM2->CNT;
|
||||
}
|
||||
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) {
|
||||
HAL_GPIO_TogglePin(GPIOA, LED5_Pin);
|
||||
UTIL_SEQ_SetTask(1<<CFG_TASK_SEND_NOTIFY, UTIL_SEQ_RFU);
|
||||
// Process data here or something
|
||||
if (huart->gState == HAL_UART_STATE_READY) {
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
HAL_UART_RxEventTypeTypeDef event = HAL_UARTEx_GetRxEventType(huart);
|
||||
|
||||
if (event == HAL_UART_RXEVENT_IDLE || event == HAL_UART_RXEVENT_TC) {
|
||||
HAL_GPIO_TogglePin(GPIOA, LED5_Pin);
|
||||
xfer_len = Size;
|
||||
memcpy(ble_out_data, uart_rx_data, Size);
|
||||
UTIL_SEQ_SetTask(1<<CFG_TASK_SEND_NOTIFY, UTIL_SEQ_RFU);
|
||||
// Process data here or something
|
||||
if (huart->gState == HAL_UART_STATE_READY) {
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
}
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
|
||||
}
|
||||
xfer_len = Size;
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
|
||||
}
|
||||
|
||||
void HAL_UART_TXCpltCallback(UART_HandleTypeDef *huart) {}
|
||||
|
||||
// tim2 is 1kHz, callback is 1Hz
|
||||
// tim2 is 1kHz, period is 1<<32 - 1X, should never get called
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
|
||||
if (htim->Instance == TIM2) {
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
}
|
||||
}
|
||||
/* USER CODE END 0 */
|
||||
|
||||
@@ -157,17 +168,26 @@ int main(void)
|
||||
/* Infinite loop */
|
||||
/* USER CODE BEGIN WHILE */
|
||||
HAL_TIM_Base_Start_IT(&htim2);
|
||||
for (uint32_t i = 0; i < 256; ++i) {
|
||||
((uint32_t*)ble_out_data)[i] = i;
|
||||
}
|
||||
UTIL_SEQ_RegTask(1<<CFG_TASK_SEND_NOTIFY, UTIL_SEQ_RFU, SendNotifyTask);
|
||||
HAL_GPIO_WritePin(GPIOA, LED4_Pin, GPIO_PIN_SET);
|
||||
HAL_GPIO_WritePin(GPIOA, LED5_Pin, GPIO_PIN_RESET);
|
||||
HAL_Delay(1000); // Give the l452 time to start up
|
||||
HAL_GPIO_WritePin(GPIOA, LED4_Pin, GPIO_PIN_RESET);
|
||||
HAL_GPIO_WritePin(GPIOA, LED5_Pin, GPIO_PIN_SET);
|
||||
__HAL_DMA_DISABLE_IT(huart1.hdmarx, DMA_IT_HT);
|
||||
__HAL_DMA_DISABLE_IT(huart1.hdmarx, DMA_IT_HT);
|
||||
HAL_UARTEx_ReceiveToIdle_DMA(&huart1, uart_rx_data, sizeof(uart_rx_data));
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
while (1)
|
||||
{
|
||||
if (TIM2->CNT - last_send > 4000) {
|
||||
if (huart1.gState == HAL_UART_STATE_READY) {
|
||||
HAL_UART_Transmit_DMA(&huart1, uart_tx_data, sizeof(uart_tx_data));
|
||||
last_send = TIM2->CNT;
|
||||
}
|
||||
}
|
||||
/* USER CODE END WHILE */
|
||||
MX_APPE_Process();
|
||||
|
||||
|
||||
Reference in New Issue
Block a user